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hd404328 series rev. 6.0 sept. 1998 description the hd404328 series is an hmcs400-series microcomputer designed to increase program productivity and also to incorporate large-capacity memory. each microcomputer has an lcd controller/driver, a/d converter, and zero-crossing detection circuit. each also has a 32.768-khz oscillator and low-power dissipation modes. the hd404328 series includes eight chips: the HD404324 and HD404324u with 4-kword rom; the hd404326 and hd404326u with 6-kword rom; the hd404328 and hd404328u with 8-kword rom; the hd4074329 and hd4074329u with 16-kword prom. the HD404324u, hd404326u, hd404328u and hd4074329u are designed to reduce current dissipation in subactive mode and watch mode. the hd4074329 and hd4074329u, which include prom, are ztat ? microcomputers that can dramatically shorten system development periods and smooth the process from debugging to mass production. (the prom program specifications are the same as for the 27256.) features 4,096-word 10-bit rom (HD404324, HD404324u) 6,144-word 10-bit rom (hd404326, hd404326u) 8,192-word 10-bit rom (hd404328, hd404328u) 16,384-word 10-bit prom (hd4074329, hd4074329u) 280-digit 4-bit ram (HD404324, HD404324u, hd404326, hd404326u, hd404328, hd404328u) 536-digit 4-bit ram (hd4074329, hd4074329u) 35 i/o pins ? 2 input pins ? 33 input/output pins, including 8 high-current pins (15 ma, max.) and 16 pins multiplexed with lcd segment pins three timer/counters 8-bit clock-synchronous serial interface 8-bit 4-channel a/d converter 12-di git lcd cont rol l er/ driver (24 s eg 4 c om ) (HD404324u, hd404326u, hd404328u, hd4074329u: external lcd voltage division resistors are required)
hd404328 series 2 zero-crossing detection circuit eight interrupt sources ? two external sources, including one double-edge function ? six internal sources subroutine stack ? up to 16 levels, including interrupts four low-power dissipation modes ? subactive mode ? standby mode ? watch mode ? stop mode built-in oscillator ? crystal or ceramic oscillator (external clock also enabled) ? 32.768 khz crystal subclock instruction cycle time: 2 m s (f osc = 4 mhz) two operating modes ? mcu mode ? prom mode (hd4074329, hd4074329u) ztat ? is a trademark of hitachi ltd.
hd404328 series 3 ordering information type product name model name rom (words) ram (digits) package mask rom HD404324 HD404324s 4,096 280 dp-64s HD404324fs fp-64b HD404324h fp-64a hd404326 hd404326s 6,144 dp-64s hd404326fs fp-64b hd404326h fp-64a hd404328 hd404328s 8,192 dp-64s hd404328fs fp-64b hd404328h fp-64a HD404324u * HD404324us 4,096 dp-64s HD404324ufs fp-64b HD404324uh fp-64a hd404326u * hd404326us 6,144 dp-64s hd404326ufs fp-64b hd404326uh fp-64a hd404328u * hd404328us 8,192 dp-64s hd404328ufs fp-64b hd404328uh fp-64a ztat ? hd4074329 hd4074329s 16,384 536 dp-64s hd4074329fs fp-64b hd4074329u * hd4074329us dp-64s hd4074329ufs fp-64b note: * type with external lcd voltage-dividing resistor.
hd404328 series 4 pin arrangement r1 / sck 0 r1 1 /si r1 2 /so r1 3 /buzz v cc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 reset 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 com4 com3 com2 com1 seg24 seg23 seg22 seg21 seg20 seg19 seg18 seg17 r5 /seg16 r5 /seg15 r5 /seg14 r5 /seg13 r4 /seg12 r4 /seg11 r4 /seg10 r4 /seg9 r3 /seg8 r3 /seg7 r3 /seg6 r3 /seg5 r2 /seg4 r2 /seg3 r2 /seg2 r2 /seg1 3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0 seg22 seg21 seg20 seg19 seg18 seg17 r5 /seg16 r5 /seg15 r5 /seg14 r5 /seg13 r4 /seg12 r4 /seg11 r4 /seg10 r4 /seg9 r3 /seg8 r3 /seg7 r3 /seg6 r3 /seg5 r2 /seg4 3 2 1 0 3 2 1 0 3 2 1 0 3 x1 x2 gnd v v v 1 2 3 av cc an an an an 0 1 2 3 av ss osc osc 1 2 d d d d d d d d 0 1 2 3 4 5 6 7 d 9 / int 0 d 10 /int 1 r0 r0 r0 r0 0 1 2 3 * reset x1 x2 gnd an an 2 3 av ss osc osc 1 2 d d d d d d d d 0 1 2 3 4 5 6 7 64 63 62 61 60 59 58 57 56 55 54 53 52 20 21 22 23 24 25 26 27 28 29 30 31 32 v v v v com4 com3 com2 com1 seg24 seg23 1 0 3 2 1 cc r2 /seg1 r2 /seg2 r2 /seg3 0 1 2 d /i nt d /int r0 r0 r0 r0 r1 / sck r1 /si r1 /so r1 /buzz 0 1 0 1 2 3 0 1 2 3 9 10 8 dp?4s fp?4b an an av (top view) cc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 seg21 seg20 seg19 seg18 seg17 r5 /seg16 r5 /seg15 r5 /seg14 r5 /seg13 r4 /seg12 r4 /seg11 r4 /seg10 r4 /seg9 r3 /seg8 r3 /seg7 r3 /seg6 av test osc osc reset x1 x2 gnd d d d d d d d d ss 1 2 0 1 2 3 4 5 6 7 64 63 62 61 60 59 58 57 56 55 54 53 52 17 18 19 20 21 22 23 24 25 26 27 28 29 3 2 1 0 cc 3 2 1 cc d / int d /int r0 r0 r0 r0 r1 / sck r1 /si r1 /so /r1 /buzz r2 /seg1 r2 /seg2 r2 /seg3 r2 /seg4 r3 /seg5 0 1 0 1 2 3 0 1 2 3 0 fp?4a 51 50 49 30 31 32 3 2 1 0 3 2 1 0 3 2 1 9 10 0 1 2 3 an an an an av v v v v com4 com3 com2 com1 seg24 seg23 seg22 * * note: d /zcd/ event * test test
hd404328 series 5 pin description pin number item symbol dp-64s dc-64s fp-64b fp-64a i/o function power supply v cc 64 58 56 applies power voltage gnd 16 10 8 connected to ground test test 10 4 2 i used for factory testing only; connect this pin to v cc reset reset 13 7 5 i resets the mcu oscillator osc 1 11 5 3 i input/output pins for the internal oscillator circuit; connect them to a crystal, ceramic, or external oscillator circuit osc 2 1264o x1 14 8 6 i used for a 32.768-khz crystal for clock purposes; if not used, fix x1 to v cc and leave x2 open x2 15 9 7 o port d 0 ? 8 17?5 11?9 9?7 i/o input/output ports addressed by individual bits; pins d 0 ? 7 are high- current pins that can each supply up to 15 ma d 9 , d 10 26, 27 20, 21 18, 19 i input ports addressable by individual bits r0 0 ?5 3 28?1 22?5 20?3 i/o input/output ports addressable in 4- bit units interrupt int 0 , int 1 26, 27 20, 21 18, 19 i input pins for external interrupts serial interface sck 32 26 24 i/o serial interface clock input/output pin si 33 27 25 i serial interface receive data input pin so 34 28 26 o serial interface transmit data output pin buzzer buzz 35 29 27 o buzzer signal output pin lcd v 1 , v 2 , v 3 1? 59?1 57?9 power pins for lcd driver; can be left open in operation because they are connected by internal voltage division resistors (except for HD404324u, hd404326u, hd404328u and hd4074329u) voltage conditions are: v cc 3 v 1 3 v 2 3 v 3 3 gnd com1?om4 60?3 54?7 52?5 o common signal pins for lcd seg1?eg24 36?9 30?3 28?1 o segment signal pins for lcd
hd404328 series 6 pin number item symbol dp-64s dc-64s fp-64b fp-64a i/o function a/d converter av cc 4 62 60 power pin for a/d converter; connect it to the same potential as v cc , as physically close as possible to the power source av ss 9 3 1 ground for av cc ; connect it to the same potential as gnd, as physically close as possible to the power source an 0 ?n 3 5? 63, 64, 1, 2 61?4 i analog input pins for 4-channel a/d converter zero- crossing detection zcd 25 19 17 i zero-crossing detection input pin counter event 25 19 17 i event count input pin
hd404328 series 7 block diagram d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 8 d 9 d 10 r0 0 r0 1 r0 2 r0 3 d port r0 port r1 0 r1 1 r1 2 r1 3 r1 port r2 0 r2 1 r2 2 r2 3 r2 port r3 0 r3 1 r3 2 r3 3 r3 port r4 0 r4 1 r4 2 r4 3 r4 port r5 0 r5 1 r5 2 r5 3 r5 port pc (14 bits) instruction decoder sp (10 bits) b (4 bits) a (4 bits) st (1 bit) ca (1 bit) alu spy (4 bits) y (4 bits) spx (4 bits) x (4 bits) w (2 bits) ram (280 4 bits) (536 4 bits) system control interrupt control timer a timer b timer c serial interface buzzer internal data bus internal data bus internal data bus buzz av an an an an av si so sck event int 0 int 1 cc 1 2 reset test osc osc x1 x2 v gnd ss 0 1 2 3 cc rom (4,096 10 bits) (6,144 10 bits) (8,192 10 bits) (16,384 10 bits) zero- crossing detection zcd lcd driver/ controller v v v com1 com2 com3 com4 seg1 seg2 seg3 seg23 seg24 1 2 3 . . . . . a/d converter data bus large-current pins directional signal line cpu
hd404328 series 8 memory map rom memory map the rom memory map is shown in figure 1 and described below. vector address zero-page subroutine (64 words) pattern (4,096 words) HD404324, HD404324u program (4,096 words) hd404328, hd404328u program (8,192 words) hd404326, hd404326u program (6,144 words) hd4074329, hd4074329u program (16,384 words) $0000 $000f $0010 $0fff $1000 $1fff $2000 $3fff 0 15 16 63 64 4095 4096 $17ff $1800 6143 6144 8191 8192 16383 jmpl instruction (jump to reset routine) jmpl instruction (jump to int 0 routine) jmpl instruction (jump to timer a routine) jmpl instruction (jump to timer b routine) jmpl instruction (jump to timer c routine) jmpl instruction (jump to zcd routine) jmpl instruction (jump to a/d, serial routines) jmpl instruction (jump to int 1 routine) $0000 $0001 $0002 $0003 $0004 $0005 $0006 $0007 $0008 $0009 $000a $000b $000c $000d $000e $000f 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 $003f $0040 figure 1 rom memory map vector address area ($0000?000f): reserved for jmpl instructions that branch to the start addresses of the reset and interrupt routines. after mcu reset or an interrupt, program execution continues from the vector address. zero-page subroutine area ($0000?003f): reserved for subroutines. the program branches to a subroutine in this area in response to the cal instruction. pattern area ($0000?0fff): contains rom data that can be referenced with the p instruction. program area (HD404324, HD404324u: $0000-$0fff; hd404326, hd404326u: $0000-$17ff; hd404328, hd404328u: $0000?1fff; hd4074329, hd4074329u: $0000?3fff): used for program coding.
hd404328 series 9 ram memory map the mpu contains a 280-digit 4-bit (HD404324, HD404324u, hd404326, hd404326u, hd404328, hd404328u) or 536-digit 4-bit (hd4074329, hd4074329u) ram area consisting of a data area and a stack area. in addition, interrupt control bits and special registers are mapped onto the same ram memory space outside this area. the ram memory map is shown in figure 2 and described below. interrupt control bits area port mode register a serial mode register serial data register, lower serial data register, upper timer mode register a timer mode register b * timer b * timer c not used miscellaneous register timer mode register c interrupt mode register port mode register b port mode register c lcd control register lcd mode register lcd output register a/d mode register a/d data register, lower a/d data register, upper register flag area not used (pmra) (smr) (srl) (sru) (tma) (tmb) (tcbl/tlrl) (tcbu/tlru) (mis) (tmc) (tccl/tcrl) (tccu/tcru) (imr) (pmrb) (pmrc) (lcr) (lmr) (lor) (amr) (adrl) (adru) w w r/w r/w w w r/w r/w w w r/w r/w w w w w w w w r r port r0 dcr port r1 dcr port r2 dcr port r3 dcr port r4 dcr port r5 dcr (dcr0) (dcr1) (dcr2) (dcr3) (dcr4) (dcr5) port d ? dcr port d ? dcr port d dcr 03 47 8 (dcrb) (dcrc) (dcrd) w w w w w w w w w not used not used w w w w r r r r timer load register b, lower (tlrl) timer load register b, upper (tlru) timer load register c, lower (tcrl) timer load register c, upper (tcru) timer/event counter b, lower (tcbl) timer/event counter b, upper (tcbu) timer counter c, lower (tccl) timer counter c, upper (tccu) $000 $001 $002 $003 $004 $005 $006 $007 $008 $009 $00a $00b $00c $00d $00e $00f $010 $011 $012 $013 $014 $015 $016 $017 $018 $020 $023 $030 $031 $032 $033 $034 $035 $03b $03c $03d $03e $03f 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 32 35 48 49 50 51 52 53 59 60 61 62 63 shaded area can only be used by the hd4074329, and hd4074329u note: two registers mapped on the same area read only write only read/write r: w: r/w: $000 $04f $050 $067 $068 $06f $070 $11f $120 $03f $040 $21f $220 $3bf $3c0 $3ff ram-mapped registers (64 digits) memory registers (mr) (16 digits) lcd display area (24 digits) not used data (176 digits) data (256 digits) not used stack (64 digits) 0 63 64 79 80 103 104 111 112 287 288 543 544 959 960 1023 $00a $00b $00e $00f * figure 2 ram memory map
hd404328 series 10 interrupt control bits area and register flag area ($000?003, $020?023): used for interrupt control bits and the bit register (figure 3). this area can be accessed only by ram bit manipulation instructions. in addition, note that the interrupt request flag cannot be set by software, the rsp bit is used only to reset the stack ppointer, and the wdon flag can be set only by the sem and semd instructions. special function registers area ($004?01f, $024?03f): used as mode registers for external interrupts, serial interface, and timer/counters, and as data registers and as data control registers for i/o ports. as shown in figure 2, these registers can be classified into three types: write-only, read-only, and read/write. the sem, semd, rem, and remd instructions can be used for the lcd control register (lcr), but ram bit manipulation instructions cannot be used for other registers. lcd data area ($050?067): used for storing lcd data which is automatically output to lcd segments as display data. data 1 lights the corresponding lcd segment; data 0 extinguishes it. data area (HD404324, HD404324u, hd404326, hd404326u, hd404328, hd404328u: $040?04f and $070?11f, hd4074329, hd4074329u: $040?04f and $070?21f): the memory registers (mr), which consist of 16 digits ($040?04f), can be accessed by the lamr and xmra instructions. its structure is shown in figure 4. stack area ($3c0?3ff): used for saving the contents of the program counter (pc), status flag (st), and carry flag (ca) at subroutine calls (cal, call) and interrupts. this area can be used as a 16-level nesting subroutine stack in which one level requires four digits. the data to be saved and the save conditions are shown in figure 4. the program counter is restored by either the rtn or rtni instruction, but the status and carry flags can only be restored by the rtni instruction. any unused space in this area is used for data storage.
hd404328 series 11 bit 3 bit 2 bit 1 bit 0 im0 (im of int ) 0 imta (im of timer a) imtc (im of timer c) imad (im of a/d) if0 (if of int ) ifta (if of timer a) iftc (if of timer c) ifad (if of a/d) rsp (reset sp bit) im1 (im of int ) imtb (im of timer b) imzc (im of zcd) ie (interrupt enable flag) if1 (if of int ) iftb (if of timer b) ifzc (if of zcd) 0 11 dton (direct transfer on flag) adsf (a/d start flag) wdon (watchdog on flag) lson (low speed on flag) ims (im of serial interface) ifs (if of serial interface) if: im: ie: sp: interrupt request flag interrupt mask interrupt enable flag stack pointer note: bits in the interrupt control bits area and register flag area are set by the sem or semd instruction, reset by the rem or remd instruction, and tested by the tm or tmd instruction. other instructions have no effect. however, note the following usage limitations of ram bit manipulation instructions. $000 $001 $002 $003 $020 $021 $022 $023 0 1 2 3 32 33 34 35 not used sem/semd not executed not executed allowed not executed in active mode used in subactive mode rem/remd allowed allowed not executed allowed tm/tmd allowed inhibited inhibited allowed if rsp wdon dton note: wdon is reset by mcu reset. dton is always reset in active mode. if the tm or tmd instruction is executed for the inhibited bits or non-existing bits, the value in st becomes invalid. figure 3 configuration of interrupt control bits and register flag areas
hd404328 series 12 memory registers mr (0) mr (1) mr (2) mr (3) mr (4) mr (5) mr (6) mr (7) mr (8) mr (9) mr (10) mr (11) mr (12) mr (13) mr (14) mr (15) level 16 level 15 level 14 level 13 level 12 level 11 level 10 level 9 level 8 level 7 level 6 level 5 level 4 level 3 level 2 level 1 stack area 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 $040 $041 $042 $043 $044 $045 $046 $047 $048 $049 $04a $04b $04c $04d $04e $04f $3c0 960 $3ff 1023 $3fc $3fd $3fe $3ff 1020 1021 1022 1023 st pc ca pc pc pc pc pc 13 9 6 2 bit 3 bit 2 bit 1 bit 0 pc ?c : st: ca: program counter status flag carry flag 13 0 10 3 pc pc pc pc 12 8 5 1 pc pc pc pc 11 7 4 0 figure 4 configuration of memory registers and stack area, and stack position
hd404328 series 13 functional description registers and flags the mcu has nine registers and two flags for cpu operations. they are shown in figure 5 and described below. 30 30 30 30 30 30 0 0 0 13 95 1 (b) (a) (w) (x) (y) (spx) (spy) (ca) (st) (pc) (sp) 1111 accumulator b register w register x register y register spx register spy register carry status program counter initial value: 0, no r/w stack pointer initial value: $3ff, no r/w 0 0 initial value: undefined, r/w initial value: undefined, r/w initial value: undefined, r/w initial value: undefined, r/w initial value: undefined, r/w initial value: undefined, r/w initial value: undefined, r/w initial value: undefined, r/w initial value: 1, no r/w figure 5 registers and flags accumulator (a), b register (b): four-bit registers used to hold results from the arithmetic logic unit (alu) and transfer data between memory, i/o, and other registers.
hd404328 series 14 w register (w), x register (x), y register (y): two-bit (w) and four-bit (x and y) registers used for indirect ram addressing. the y register is also used for d-port addressing. spx register (spx), spy register (spy): four-bit registers used to supplement the x and y registers. carry flag (ca): one-bit flag that stores any alu overflow generated by an arithmetic operation. ca is affected by the sec, rec, rotl, and rotr instructions. a carry is pushed onto the stack during an interrupt and popped from the stack by the rtni instruction?ut not by the rtn instruction. status flag (st): one-bit flag that latches any overflow generated by an arithmetic or compare instruction, not-zero decision from the alu, or result of a bit test. st is used as a branch condition of the br, brl, cal, and call instructions. the contents of st remain unchanged until the next arithmetic, compare, or bit test instruction is executed, but become 1 after the br, brl, cal, or call instruction is read, regardless of whether the instruction is executed or skipped. the contents of st are pushed onto the stack during an interrupt and popped from the stack by the rtni instruction?ut not by the rtn instruction. program counter (pc): a 14-bit counter that points to the rom address of the instruction being executed. stack pointer (sp): ten-bit pointer that contains the address of the stack area to be used next. the sp is initialized to $3ff by mcu reset, is decremented by 4 when data is pushed onto the stack, and is incremented by 4 when data is popped from the stack. since the top four bits of the sp are fixed at 1111, a stack of up to 16 levels can be used. the sp can be initialized to $3ff in another way: by resetting the rsp bit with the rem or remd instruction.
hd404328 series 15 reset the mcu is reset by inputting a high-level voltage to the reset pin. at power-on or when stop mode is cancelled, reset must be high for at least one t rc to enable the oscillator to stabilize. during operation, reset must be high for at least two instruction cycles. initial values after mcu reset are shown in table 1. table 1 initial values after mcu reset item abbr. initial value contents program counter (pc) $0000 indicates program execution point from start address of rom area status flag (st) 1 enables conditional branching stack pointer (sp) $3ff stack level 0 interrupt flags/mask interrupt enable flag (ie) 0 inhibits all interrupts interrupt request flag (if) 0 indicates there is no interrupt request interrupt mask (im) 1 prevents (masks) interrupt requests i/o port data register (pdr) all bits 1 enables output at level 1 data control register (dcr) all bits 0 turns output buffer off (to high impedance) port mode register a (pmra) 0000 refer to description of port mode register a port mode register b (pmrb) - - 00 refer to description of port mode register b port mode register c (pmrc) 0000 refer to description of port mode register c interrupt mode register (imr) 0000 refer to description of interrupt mode register timer/ counters, serial interface timer mode register a (tma) 0000 refer to description of timer mode register a timer mode register b (tmb) 0000 refer to description of timer mode register b timer mode register c (tmc) 0000 refer to description of timer mode register c serial mode register (smr) 0000 refer to description of serial mode register prescaler s $000 prescaler w $00 timer counter a (tca) $00 timer counter b (tcb) $00
hd404328 series 16 item abbr. initial value contents timer/ counters, serial interface timer counter c (tcc) $00 timer load register b (tlr) $00 timer load register c (tcr) $00 octal counter 000 a/d a/d mode register (amr) 00-0 refer to description of a/d mode register lcd lcd control register (lcr) 000 refer to description of lcd control register lcd mode register (lmr) 0000 refer to description of lcd duty cycle/clock control register lcd output register (lor) 0000 refer to description of lcd output register bit register low speed on flag (lson) 0 refer to description of low-power dissipation modes watchdog timer on flag (wdon) 0 refer to description of timer c a/d start flag (adsf) 0 refer to description of a/d converter direct transfer on flag (dton) 0 refer to description of low-power dissipation modes miscellaneous register (mis) 0000 refer to description of miscellaneous register note: the statuses of other registers and flags after mcu reset are as follows: item abbr. status after cancellation of stop mode by mcu reset status after cancellation of all other types of modes by mcu reset carry flag (ca) pre-mcu-reset values are not guaranteed: values must be initialized by program pre-mcu-reset values are not guaranteed: values must be initialized by program accumulator (a) b register (b) w register (w) x/spx register (x/spx) y/spy register (y/spy) serial data register (sr) a/d data register (adrl, adru) ram pre-mcu-reset (pre-stop- instruction) values are retained
hd404328 series 17 interrupts the mcu has eight interrupt sources: two external signals ( int 0 and int 1 ), three timer/counters (timer a, timer b, and timer c), serial interface, zero-crossing detection, and a/d converter. an interrupt request flag (if), interrupt mask (im), and vector address are provided for each interrupt source, and an interrupt enable flag (ie) controls the entire interrupt process. vector addresses are shared by serial interface and a/d converter interrupt causes, so software must first check which type of request has occurred. interrupt control bits and interrupt servicing: locations $000?003 and $020?023 in ram are reserved for the interrupt control bits which can be accessed by ram bit manipulation instructions. the interrupt request flag (if) cannot be set by software. mcu reset initializes the interrupt enable flag (ie) and the if to 0 and the interrupt mask (im) to 1. a block diagram of the interrupt control circuit is shown in figure 6, interrupt priorities and vector addresses are listed in table 2, and interrupt processing conditions for the eight interrupt sources are listed in table 3. an interrupt request occurs when the if is set to 1 and the im is set to 0. if the ie is 1 at that point, the interrupt is processed. priority control logic generates the vector address assigned to that interrupt source. the interrupt processing sequence is shown in figure 7 and an interrupt processing flowchart is shown in figure 8. after an interrupt is acknowledged, the previous instruction is completed in the first cycle. the ie is reset in the second cycle, the carry flag, status flag, and program counter values are pushed onto the stack during the second and third cycles, and the program jumps to the vector address to execute the instruction in the third cycle. program the jmpl instruction at each vector address, to branch the program to the start address of the interrupt program, and reset the if by a software instruction within the interrupt program.
hd404328 series 18 $000, 2 $000, 3 if0 im0 $001, 0 $001, 1 if1 im1 $001, 2 $001, 3 ifta imta $002, 0 $002, 1 iftb imtb $002, 2 $002, 3 iftc imtc $003, 0 $003, 1 ifzc imzc $003, 2 $003, 3 ifad imad $000, 0 ie $023, 2 $023, 3 ifs ims sequence control ? push pc/ca/st ? reset ie ? jump to vector address priority control logic vector address note: $m, n is ram address $m, bit number n. int interrupt timer a interrupt timer b interrupt timer c interrupt 0 int interrupt 1 zcd interrupt a/d interrupt serial interrupt figure 6 block diagram of interrupt control circuit
hd404328 series 19 table 2 vector addresses and interrupt priorities reset/interrupt priority vector address reset $0000 int 0 1 $0002 int 1 2 $0004 timer a 3 $0006 timer b 4 $0008 timer c 5 $000a zcd 6 $000c a/d, serial 7 $000e table 3 interrupt processing and activation conditions interrupt cause interrupt control bit int 0 int 1 timer a timer b timer c zcd a/d, serial ie 1 1 1 1 1 1 1 if0 . im0 100 0000 if1 . im1 * 10 0 0 00 ifta . imta ** 10000 iftb . imtb *** 10 00 iftc . imtc *** * 100 ifzc . imzc *** ** 10 ifad . imad + ifs . ims *** *** 1 note: bits marked * can be either 0 or 1. their values have no effect on operation.
hd404328 series 20 instruction cycles 12 34 5 6 instruction execution interrupt acceptance stacking; ie reset stacking; vector address generation execution of jmpl instruction at vector address execution of instruction at start address of interrupt routine the stack is accessed and the ie reset after the instruction is executed, even if it is a two-cycle instruction. figure 7 interrupt processing sequence
hd404328 series 21 power on reset=1? reset mcu interrupt request? no yes no no yes yes no no no no no yes yes yes yes yes (a/d, serial interrupt) execute instruction pc ? (pc) + 1 pc ? $0002 pc ? $0004 pc ? $0006 pc ? $0008 pc ? $000a pc ? $000c pc ? $000e ie = 1? accept interrupt yes ie ? 0 stack ? (pc) stack ? (ca) stack ? (st) int 0 interrupt? int 1 interrupt? timer a interrupt? timer b interrupt? timer c interrupt? zcd interrupt? no figure 8 interrupt processing flowchart
hd404328 series 22 interrupt enable flag (ie: $000, bit 0): controls the entire interrupt process. it is reset by the interrupt processing and set by the rtni instruction, as shown in table 4. table 4 interrupt enable flag ie interrupt enabled/disabled 0 disabled 1 enabled external interrupts ( int 0 , int 1 ): specified by port mode register a (pmra: $004). external interrupt request flags (if0: $000, bit 2; if1: $001, bit 0): set at the rising or falling edges of the int 0 and int 1 inputs, as shown in table 5. table 5 external interrupt request flags if0, if1 interrupt request 0no 1 yes if0 is set at the falling edge of signals input to int 0 , and if1 is set at the rising and falling edges of signals input to int 1 . the int 1 interrupt edge is selected by the interrupt mode register (imr: $010), as shown in figure 9. interrupt mode register (imr): $010 3210 int detection edge selection 1 zcd detection edge selection imr bit 3 bit 2 0 1 0 1 0 1 zcd detection edge no detection falling-edge detection rising-edge detection double-edge detection imr bit 1 bit 0 0 1 0 1 0 1 int detection edge no detection falling-edge detection rising-edge detection double-edge detection 1 initial value: 0000, r/w: w figure 9 interrupt mode register
hd404328 series 23 external interrupt masks (im0: $000, bit 3; im1: $001, bit 1): prevent (mask) interrupt requests caused by the corresponding external interrupt request flags, as shown in table 6. table 6 external interrupt masks im0, im1 interrupt request 0 enabled 1 disabled (masked) timer a interrupt request flag (ifta: $001, bit 2): set by overflow output from timer a, as shown in table 7. table 7 timer a interrupt request flag ifta interrupt request 0no 1 yes timer a interrupt mask (imta: $001, bit 3): prevents (masks) an interrupt request caused by the timer a interrupt request flag, as shown in table 8. table 8 timer a interrupt mask imta interrupt request 0 enabled 1 disabled (masked) timer b interrupt request flag (iftb: $002, bit 0): set by overflow output from timer b, as shown in table 9. table 9 timer b interrupt request flag iftb interrupt request 0no 1 yes
hd404328 series 24 timer b interrupt mask (imtb: $002, bit 1): prevents (masks) an interrupt request caused by the timer b interrupt request flag, as shown in table 10. table 10 timer b interrupt mask imtb interrupt request 0 enabled 1 disabled (masked) timer c interrupt request flag (iftc: $002, bit 2): set by overflow output from timer c, as shown in table 11. table 11 timer c interrupt request flag iftc interrupt request 0no 1 yes timer c interrupt mask (imtc: $002, bit 3): prevents (masks) an interrupt request caused by the timer c interrupt request flag, as shown in table 12. table 12 timer c interrupt mask imtc interrupt request 0 enabled 1 disabled (masked) zero-crossing interrupt request flag (ifzc: $003, bit 0): set by a zero crossing of an ac input signal, as shown in table 13. the interrupt edge is selected by the interrupt mode register (imr: $010), as shown in figure 9. table 13 zero-crossing interrupt request flag ifzc interrupt request 0no 1 yes zero-crossing interrupt mask (imzc: $003, bit 1): prevents (masks) an interrupt request caused by the zero-crossing interrupt request flag, as shown in table 14.
hd404328 series 25 table 14 zero-crossing interrupt mask imzc interrupt request 0 enabled 1 disabled (masked) a/d interrupt request flag (ifad: $003, bit 2): set at the completion of a/d conversion, as shown in table 15. table 15 a/d interrupt request flag ifad interrupt request 0no 1 yes a/d interrupt mask (imad: $003, bit 3): prevents (masks) an interrupt request caused by the a/d interrupt request flag, as shown in table 16. table 16 a/d interrupt mask imad interrupt request 0 enabled 1 disabled (masked) serial interrupt request flag (ifs: $023, bit 2): set when the octal counter counts the eighth transmit clock signal or when data transfer is discontinued by resetting the octal counter (table 17). table 17 serial interrupt request flag ifs interrupt request 0no 1 yes serial interrupt mask (ims: $023, bit 3): prevents (masks) an interrupt request caused by the serial interrupt request flag, as shown in table 18. table 18 serial interrupt mask ims interrupt request 0 enabled 1 disabled (masked)
hd404328 series 26 operating modes the mcu has five operating modes that are specified by how the clock is used. the functions available in each mode are listed in table 19, and operations are shown in table 20. transitions between operating modes are shown in figure 10. table 19 functions available in each operating mode mode name active standby stop watch subactive * 4 activation method reset cancellation, interrupt request sby instruction tma3 = 0 stop instruction tma3 = 1 stop instruction int 0 or timer a interrupt request from watch mode status system oscillator op op stopped stopped stopped subsystem oscillator op op * 1 op op op instruction execution ( cpu ) op stopped stopped stopped op interrupt function interrupt ( per ) op op stopped stopped * 5 op clock function interrupt ( clk ) op op stopped * 2 op * 2 op ram op retained retained retained op registers/flags op retained reset * 6 retained retained/ operating i/o op retained reset * 3 retained op cancellation method reset input, stop/sby instruction reset input interrupt request reset input reset input, int 0 or timer a interrupt request reset input, stop/sby instruction notes: op: indicates in operation 1. to reduce current dissipation, stop all oscillation in external circuits. 2. refer to the interrupt frame section for details. 3. output pins are at high impedance. 4. subactive mode is an optional function; specify it on the function option list. 5. the a/d converter does not operate. 6. port mode register b retains the contents it had in active mode.
hd404328 series 27 system clock ( cpu ) operating stopped non-time-base peripheral function clock ( per ) operating active mode standby mode subactive mode stopped watch mode (tma3 = 1) stop mode (tma3 = 0) table 20 operations in low-power dissipation modes function stop mode watch mode standby mode subactive mode * 3 cpu reset retained retained op ram retained retained retained op timer a reset op op op timer b reset stopped op op timer c reset stopped op op serial interface reset stopped * 3 op op lcd reset op op op i/o reset * 1 retained retained op a/d reset stopped op stopped zero-crossing detection stopped * 4 stopped * 4 op op notes: op: indicates in operation 1. output pins are at high impedance. 2. subactive mode is an optional function specified on the function option list. 3. transmission/reception is activated if a clock is input in external clock mode. (however interrupts stop.) 4. the bias circuits still operate when the d 8 /zcd/ event pin is set to zcd.
hd404328 series 28 standby mode active mode reset stop mode (tma3 = 0) ? osc : f x : ? cpu : ? clk : ? per : operating operating stopped f cyc f cyc ? osc : f x : ? cpu : ? clk : ? per : operating operating stopped f sub f cyc sby (standby) sby (standby) interrupt notes: ? osc : f x : ? cpu : ? clk : ? per : operating operating f cyc f sub f cyc ? osc : f x : ? cpu : ? clk : ? per : ? osc : f x : ? cpu : ? clk : ? per : operating operating f f cyc f cyc stopped operating f sub f sub f sub ? osc : f x : ? cpu : ? clk : ? per : stopped operating stopped stopped stopped ? osc : f x : ? cpu : ? clk : ? per : stopped operating stopped f sub stopped ? osc : f x : ? cpu : ? clk : ? per : stopped operating stopped f sub stopped watch mode (tma3 = 1, lson = 0) (tma3 = 1, lson = 1) stop stop int 0, time-base stop * 3 subactive mode int 0 , time-base stop/sby (lson = 1) (tma3 = 0) (tma3 = 1) ? osc : f x : f cyc : f sub : ? cpu : ? clk : ? per : lson: dton: main oscillation frequency suboscillation frequency, for time-base f osc /8 f x /8 system clock clock for time-base clock for other peripheral functions low speed on flag direct transfer on flag 1. interrupt source 2. stop/sby (dton = 1, lson = 0) 3. stop/sby (dton = 0, lson = 0) 4. dton can be 0 or 1. interrupt cyc * 1 * 4 * 1 * 2 figure 10 mcu status transitions active mode: the mcu operates according to the clock generated by the system oscillators osc 1 and osc 2 . standby mode: the mcu enters standby mode when the sby instruction is executed from active mode. in this mode, the oscillators, interrupts, timer/counters, and serial interface continue to operate, but all instruction execution-related clocks stop. the stopping of these clocks stops the cpu, retaining all ram and register contents and maintaining the current i/o pin status. the standby mode is terminated by a reset input or an interrupt request. if it is terminated by reset input, the mcu is reset as well. after an interrupt request, the mcu enters active mode and resumes, executing the next instruction after the sby instruction. if the interrupt enable flag is 1, that interrupt is then processed; if it is 0, the interrupt request is left pending and normal instruction execution continues. a flowchart of operation in standby mode is shown in figure 11.
hd404328 series 29 standby watch oscillator: active peripheral clocks: active all other clocks: stopped oscillator: stopped sub-oscillator: active peripheral clocks: stopped all other clocks: stopped reset = 1? no no no no no yes yes yes no yes no yes yes if0 = 1? im0 = 0? if1 = 1? im1 = 0? ifta = 1? imta = 0? iftb = 1? imtb = 0? iftc = 1? imtc = 0? yes no yes no no yes no yes no yes yes no yes no no yes yes no no yes ifzc = 1? imzc = 0? ifad = 1? imad = 0? ifs = 1? ims = 0? (sby only) (sby only) (sby only) (sby only) (sby only) (sby only) restart processor clocks execute next instruction restart processor clocks if = 1, im = 0, ie = 1? no yes execute next instruction accept interrupt reset mcu yes figure 11 mcu operation flowchart
hd404328 series 30 stop mode: the mcu enters stop mode if the stop instruction is executed in active mode when tma3 = 0. in this mode, the system oscillator stops, which stops all mcu functions as well. the stop mode is terminated by a reset input as shown in figure 12. reset must be high for at least one t rc to stabilize oscillation (refer to the ac characteristics section). when the mcu restarts after stop mode is cancelled, all ram contents are retained, but the accuracy of the contents of the accumulator, b register, w register, x/spx register, y/spy register, carry flag, and serial data register cannot be guaranteed. stop mode oscillator internal clock reset stop instruction execution t res t rc 3 (stabilization time) res t figure 12 timing of stop mode cancellation watch mode: the mcu enters watch mode if the stop instruction is executed in active mode when tma3 = 1, or if the stop or sby instruction is executed in subactive mode. the watch mode is terminated by a reset input or a timer-a/ int 0 interrupt request. for details of reset input, refer to the stop mode section. when terminated by a timer-a/ int 0 interrupt request, the mcu enters active mode if lson is 0, or subactive mode if lson is 1. after an interrupt request is generated, the time required to enter active mode is t rc for a timer a interrupt, and t x (where t + t rc < t x < 2t + t rc ) for an int 0 interrupt, as shown in figures 13 and 14.
hd404328 series 31 t rc t t x t t: t : interrupt frame length oscillation stabilization period rc (during the transition from watch mode to active mode only) interrupt strobe int 0 interrupt request generation active mode watch mode active mode oscillation stabilization period figure 13 interrupt frame 3210 t selection rc r1 /so pmos off 2 setting for switching the system oscillator? frequency miscellaneous register (mis): $00c bit 1 bit 0 mis t 1 t rc 0.24414 ms 0.12207 ms 0.24414 ms 7.8125 ms 62.5 ms 15.625 ms 125 ms not used 00 0 1 1 1 0 1 t: t : rc interrupt frame length oscillation stabilization period notes: 1. 2. the value of t applies only when using a 32.768-khz crystal oscillator. only direct transfer. rc * 1 * 2 * initial value: 0000, r/w: w figure 14 miscellaneous register
hd404328 series 32 operation during mode transition is the same as that at standby mode cancellation (figure 11). subactive mode: the cpu operates with a clock generated by the x1 and x2 oscillation circuits. functions that can operate in subactive mode are listed in table 20. when the stop or sby instruction is executed in subactive mode, the mcu enters either watch or active mode, depending on the statuses of lson and dton. the dton flag can only be set in subactive mode; it is automatically reset after a transition to active mode. the subactive mode is an optional function that the user must specify on the function option list. interrupt frame : in watch and subactive modes, timer a and int 0 interrupts are generated in synchronism with the interrupt frame. three interrupt frame lengths (t) can be selected by the settings of the miscellaneous register, as shown in figure 14. the time from an interrupt strobe to interrupt request generation is the oscillation stabilization period (t rc ), as shown in figure 13. the interrupt request is generated synchronously with the interrupt strobe timing except during transition to active mode. the falling edge of the int 0 signal is input asynchronously with the interrupt frame timing, but it is regarded as input synchronously with the second interrupt strobe clock after the falling edge. an overflow and interrupt request in timer a is generated synchronously with the interrupt strobe timing. operation during the transition from watch mode to active mode is the same as that at standby mode cancellation (figure 11). direct transfer: by controlling the dton flag, the mcu will be placed directly from subactive to active mode. the detailed procedure is as follows: set the dton flag in subactive mode while lson = 0 and dton = 1. execute the stop or sby instruction. after the oscillation stabilization time (a fixed value), the mcu will move automatically from subactive to active mode (see figure 15). note that dton ($020, bit 3) is valid only in subactive mode. when the mcu is in active mode, this flag is always at reset. the transition time (t d ) from subactive to active mode is t rc < t d < t + t rc .
hd404328 series 33 internal execution time oscillation stabilization time active mode subactive mode (lson = 0, dton = 1) stop/sby execution t t rc interrupt strobe direct transfer timing t: t : rc interrupt frame length oscillation stabilization period figure 15 direct transfer timing mcu operation sequence: the mcu operates in the sequence shown in figures 16 to 18. it is reset by an asynchronous reset input, regardless of its state. the low-power mode operation sequence is shown in figure 18. with the ie flag cleared and an interrupt flag set together with its interrupt mask cleared, if a stop/sby instruction is executed, the instruction is cancelled (regarded as an nop) and the following instruction is executed. before executing a stop/sby instruction, make sure all interrupt flags are cleared or all interrupts are masked. power on reset = 1? reset mcu mcu operation cycle no yes figure 16 mcu operating sequence (power on)
hd404328 series 34 mcu operation cycle if = 1? yes no no yes im = 0, ie = 1? ie ? 0; stack ? (pc), (ca), (st) pc ? vector address instruction execution yes sby, stop instruction? no pc ? next location low-power mode operation cycle if: im: ie: pc: ca: st: interrupt request flag interrupt mask interrupt enable flag program counter carry flag status flag figure 17 mcu operating sequence (mcu operation cycle)
hd404328 series 35 low-power mode operation cycle if = 1, im = 0? no yes no yes standby/watch mode stop mode if = 1, im = 0? hardware nop execution instruction execution pc next location ? pc next location ? hardware nop execution mcu operation cycle for if and im operation, refer to figure 11. figure 18 mcu operating sequence (low-power mode operation) limitation on use in subactive mode, the timer a interrupt request or the external interrupt request ( int 0 ) occurs in synchronism with the interrupt strobe. if the stop or sby instruction is executed at the same time with the interrupt strobe, these interrupt requests will be cancelled and its corresponding interrupt request flags (ifta, if0) will be not set. in subactive mode, do not use the stop or sby instruction at the time of the interrupt strobe.
hd404328 series 36 when the mcu is in watch mode or subactive mode, if the high level period before the falling edge of int 0 is shorter than the interrupt frame, int 0 is not detected. also, if the low level period after the falling edge of int 0 is shorter than the interrupt frame, int 0 is not detected. edge detection is shown in figure 19. the level of the int 0 signal is sampled by a sampling clock. when this sampled value changes to low from high, a falling edge is detected. in figure 20, the level of the int 0 signal is sampled by an interrupt frame. in (a) the sampled value is low at point a, and also low at point b. therefore, a falling edge is not detected. in (b), the sampled value is high at point a, and also high at point b. a falling edge is not detected in this case either. when the mcu is in watch mode or subactive mode, keep the high level and low level period of int 0 longer than interrupt frame. int sampling 0 high low low figure 19 edge detection a: low b: low int 0 interrupt frame a. high level period a: high b: high int 0 interrupt frame b. low level period figure 20 sampling example
hd404328 series 37 internal oscillator circuit a block diagram of the internal oscillator circuit is shown in figure 22. as shown in table 21, crystal and ceramic oscillators can be connected to osc 1 and osc 2 , and a 32.768-khz oscillator can be connected to x1 and x2. the system oscillator can also be operated by an external clock. bit 3 of the miscellaneous register (mis: $00c) must be set according to the frequency of the oscillator connected to osc 1 and osc 2 . note: if the mis register setting does not match the oscillator frequency, subsystems using 32-khz oscillation will malfunction. set the system oscillator frequency to anything outside the range of 1.0 mhz to 1.6 mhz when using 32-khz oscillation. 3210 t selection rc r1 /so pmos off 2 setting for switching the system oscillator? frequency miscellaneous register (mis): $00c system oscillator? frequency mis bit 3 0 1 1.6 mhz to 4.5 mhz 0.4 mhz to 1.0 mhz initial value: 0000, r/w: w figure 21 miscellaneous register system oscillator sub-system oscillator divide-by-8 circuit divide-by-8 circuit timing generator circuit timing generator circuit synch. (t ) cyc synch. (t ) subcyc mode control circuit system clock ( ) cpu system clock ( ) per time-base clock ( ) clk osc 2 osc 1 x1 x2 figure 22 internal oscillator circuit
hd404328 series 38 table 21 oscillator circuit examples circuit configuration circuit constants external clock operation (osc , osc ) 12 external oscillator open osc 1 osc 2 osc 1 osc 2 1 c r ceramic 2 c gnd ceramic oscillator (osc , osc ) 1 2 osc 1 osc 2 1 c r crystal 2 c gnd at-cut parallel resonance crystal c 0 c s l r s osc 1 osc 2 x1 x2 1 c crystal 2 c gnd c 0 c s l r s x2 x1 crystal oscillator (osc , osc ) 12 crystal oscillator (x1, x2) ceramic: csa4.00mg (murata) r = 1 m 20% c = c = 30 pf 20% f 1 2 r : 1 m c = c = 10 pf 10% crystal: equivalent to circuit shown at bottom left c = 7 pf, max. r = 100 , max. f = 1.0 mhz to 4.5 mhz f 1 2 0 s c =c = 15 pf 5% crystal: 32.768 khz, mx38t (nippon denpa) c = 1.5 pf, typ. r = 14 k , typ. 12 0 s notes: 1. 2. 3. circuit constants differ with different types of crystal and ceramic oscillators, and with the stray capacitance of the board, so consult the manufacturer of the oscillator to determine the circuit parameters. the wiring between the osc and osc pins (x1 and x2 pins) and the other elements should be as short as possible, and must not cross other wiring. refer to figure 23. if not using a 32.768-khz crystal oscillator, fix the x1 pin to v and leave the x2 pin open. 12 cc f f w 20%
hd404328 series 39 d gnd x2 x1 reset osc osc test av 0 2 1 ss figure 23 typical layout of crystal and ceramic oscillators
hd404328 series 40 input/output the mcu has 2 input pins and 33 input/output pins, 8 of the input/output pins being large-current pins (15 ma, max.). a program-controlled pull-up mos transistor is provided for each input/output pin. the output buffer is turned on and off by the data control register (dcr) during input through an input/output pin. i/o pin circuit types are shown in table 22. table 22 circuit configurations of i/o pins int 1 i/o pin type circuit applicable pins common i/o pin (with pull-up mos transistor) output pin (with pull-up mos transistor) input pin zcd so buzz r 0 0 ? 0 3 r 1 0 ? 1 3 r 2 0 ? 2 3 r 3 0 ? 3 3 r 4 0 ? 4 3 r 5 0 ? 5 3 d 9 d 10 int 0 event si pull-up control signal output data input data input control v cc pull-up control signal output data sck (internal) pull-up control signal output data so or buzz input control input data ac input signal external capacitor sck sck note: for details of the r1 /so pin, refer to note 2 of table 23. 2 d 0 ? 8 dcr pdr dcr dcr zero-crossing detection circuit v cc v cc v cc v cc v cc pull-up control signal pdr v cc
hd404328 series 41 d port (d 0 ? 10 ): consist of 9 input/output pins and 2 input pins. pins d 0 ? 7 are high-current i/o pins, d 8 is an ordinary input/output pin, and d 9 and d 10 are input-only pins. these pins are set by the sed and sedd instructions, reset by the red and redd instructions, and tested by the td and tdd instructions. the operating modes of d 8 ? 10 are set by bits 2 and 3 of port mode register a (pmra) and bits 0 and 1 of port mode register b (pmrb), as shown in figure 24. the on/off status of the output buffer is controlled by d port data control registers (dcrb, dcrc, and dcrd) that are mapped to memory addresses. r ports: accessed in 4-bit units. data is input to these ports by the lar and lbr instructions and output from them by the lra and lrb instructions. the on/off status of the output buffers of the r ports are controlled by r port data control registers (dcr0?cr5) that are mapped to memory addresses. pins r1 0 ?1 3 are multiplexed with pins sck , si, so, and buzz, respectively. the operating modes of these pins are controlled by bit 3 of the serial mode register (smr), bits 1 and 0 of port mode register a (pmra), and bit 2 of port mode register c (pmrc), as shown in figure 24. ports r2?5 are multiplexed with seg1?eg16. the functions of these pins must be specified by the lcd output register (lor: $015).
hd404328 series 42 3210 port mode register a (pmra): $004 r1 /so pin mode selection 2 3210 serial mode register (smr): $005 r1 / sck pin mode selection 0 r1 /si pin mode selection 1 d / int pin mode selection 90 d /int pin mode selection 10 1 smr bit 3 0 1 r1 sck 0 port selection pmra bit 3 pmra bit 2 pmra bit 1 pmra bit 0 port selection port selection port selection port selection 0 1 d int 0 1 0 1 0 1 10 1 d int 9 0 r1 si 1 r1 so 2 3210 port mode register b (pmrb): $011 d /zcd/ event pin mode selection not used 8 pmrb bit 1 bit 0 port selection 0 1 0 1 0 1 zcd (low sensitivity) zcd (high sensitivity) d event 8 note: becomes low sensitivity in subactive mode. * * initial value: 0000, r/w: w initial value: 0000, r/w: w initial value: 0000, r/w: w figure 24 i/o switching mode registers
hd404328 series 43 3210 port mode register c (pmrc): $012 buzz output frequency selection 3 r1 /buzz pin mode selection pull-up mos transistor on/off selection 3210 lcd output register (lor): $015 pmrc bit 3 pmrc bit 3 port selection pull-up mos on/off selection 0 1 off on 0 1 r1 buzz 3 r2/seg1?eg4 pin mode selection r3/seg5?eg8 pin mode selection r4/seg9?eg12 pin mode selection r5/seg13?eg16 pin mode selection lor bit 3 0 1 port selection port selection port selection port selection lor bit 2 0 1 lor bit 1 0 1 lor bit 0 0 1 r5 seg13?eg16 r4 seg9?eg12 r3 seg5?eg8 r2 seg1?eg4 initial value: 0000, r/w: w initial value: 0000, r/w: w figure 24 i/o switching mode registers (cont) pull-up mos transistor control: a program-controlled pull-up mos transistor is provided for each input/output pin. the on/off status of all these transistors is controlled by bit 3 of port mode register c (pmrc), and the on/off status of an individual transistor can also be controlled by the port data register of the corresponding pin?nabling on/off control of that pin alone. the on/off status of each transistor and the peripheral function mode of each pin can be set independently. the configuration of the i/o buffer is shown in figure 25, and the configurations of various program- controlled i/o circuits are given in table 23. how to deal with unused i/o pins: i/o pins that are not needed by the user system (floating) must be connected to v cc to prevent lsi malfunctions due to noise. these pins must either be pulled up to v cc by their pull-up mos transistors or by resistors of about 100 k w .
hd404328 series 44 pmrc3 dcr pdr input data v cc v cc pmos (a) nmos (b) input control pull-up mos transistor figure 25 i/o buffer configuration table 23 programmable i/o circuits pmrc, bit 3 dcr pdr cmos buffer pmos (a) nmos (b) pull-up mos transistor 1 0 off off off 1 off off off 0 off on off 1 on off off 0 off off off 1 off off on 0 off on off 1 on off on 0 0 0 1 1 notes: 1. 2. 3. various i/o methods can be selected by different combinations of settings of the above mode registers (pmrc3, dcr, pdr). the pmos (a) transistor of the r1 /so pin can be turned off by setting bit 2 of the miscellaneous register (mis) to 1. the relationships between dcrs and pins are as shown on the right. mis bit 2 0 1 on off r1 /so pin pmos (a) 2 dcr dcr0 dcr1 dcr2 dcr3 dcr4 dcr5 dcrb dcrc dcrd bit 3 r0 r1 r2 r3 r4 r5 d d bit 2 bit 1 bit 0 3 3 3 3 3 3 3 7 2 2 2 2 2 2 1 1 1 1 1 1 0 0 0 0 0 0 2 6 1 5 0 4 8 2 r0 r1 r2 r3 r4 r5 r0 r1 r2 r3 r4 r5 d d r0 r1 r2 r3 r4 r5 d d d d d
hd404328 series 45 timers the mcu has two prescalers (s and w) and three timer/counters (a, b, and c). prescaler s: eleven-bit counter that inputs a system clock signal. after being initialized to $000 by mcu reset, prescaler s divides the system clock. prescaler s keeps counting, except in watch and stop modes, and at mcu reset. of the prescaler s outputs, timer a input clock, timer b input clock, timer c input clock, and serial interface transmit clock are selected by timer mode register a (tma), timer mode register b (tmb), timer mode register c (tmc), and the serial mode register (smr). prescaler w: five-bit counter that inputs the x1 input clock signal divided by eight. prescaler w output can be selected as a timer a input clock by timer mode register a (tma). timer a: eight-bit timer that can be used as a clock time-base (figure 26). it is initialized to $00 and incremented at each input clock. if an input clock is applied to timer a after it has reached $ff, an overflow that sets the timer a interrupt request flag (ifta: $001, bit 2) is generated, and timer a restarts from $00. timer a is used to generate regular interrupts (every 256 clocks) for measuring times between events. it can also be used as a clock time-base when bit 3 of timer mode register a (tma) is set to 1. the timer is driven by the 32-khz oscillator clock frequency divided by prescaler w, and the clock input to timer a is controlled by tma. in this case, prescaler w and timer a can be initialized to $00 by software. 1/4 1/2 32.768-khz oscillator system clock prescaler w (psw) selector selector prescaler s (pss) selector internal data bus timer a interrupt request flag (ifta) clock overflow timer counter a (tca) timer mode register a (tma) 3 2 f 1/2 tw cyc f tw cyc per 2 4 8 32 128 512 1024 2048 ? ? ? ? ? ? ? ? 2 8 16 32 ? ? ? ? w w figure 26 timer a block diagram
hd404328 series 46 timer b (tcbl and tlrl: $00a, tcbu and tlru: $00b): eight-bit write-only timer load register (tlrl and tlru) and read-only timer counter (tcbl and tcbu) located at the same addresses. the eight-bit configuration consists of lower and upper digits located at sequential addresses. a block diagram of timer b is shown in figure 27. timer counter b is initialized by writing to timer load register b (tlr). in this case, the lower nibble must be written to first. the contents of tlr are loaded into the timer counter at the same time the upper nibble is written to, initializing the timer counter. tlr is initialized to $00 by mcu reset. the count of timer b is obtained by reading timer counter b. in this case, the upper digit must be read first; the count is latched when the upper nibble is read. an auto-reload function, input clock source, and prescaler division ratio of timer b depend on the state of timer mode register b (tmb). when an external event input is used as the input clock source of tmb, the d 8 /zcd/ event pin must be set to function as the zcd or event pin by setting port mode register b (pmrb: $011). timer b is initialized to the value set in tmb by software, and is then incremented by one by each clock input. if an input is applied to timer b after it has reached $ff, an overflow is generated. in this case, if the auto-reload function is enabled, timer b is initialized to its initial value; if auto-reload is disabled, the timer is initialized to $00. the overflow sets the timer b interrupt request flag (iftb: $002, bit 0). timer/counter b (tcb) event selector system clock per prescaler s (pss) 3 timer load register b lower (tlrl) timer mode register b (tmb) timer load register b upper (tlru) clock free-running/ reload timer control signal timer latch register b (tlb) interrupt request flag of timer b (iftb) overflow internal data bus ? ? ? ? ? ? ? 2 4 8 32 128 512 2048 figure 27 timer b free-running and reload operation block diagram
hd404328 series 47 timer c (tccl and tcrl: $00a, tccu and tcru: $00b): eight-bit write-only timer load register (tcrl and tcru) and read-only timer counter (tccl and tccu) located at the same addresses. the eight-bit configuration consists of lower and upper digits located at sequential addresses. the operation of timer c is basically the same as that of timer b. a block diagram of timer c is shown in figure 28. the auto-reload function and prescaler division ratio of timer c depend on the state of timer mode register c (tmc). timer c is initialized to the value set in tmc by software, then is incremented by one at each clock input. if an input is applied to timer c after it has reached $ff, an overflow is generated. in this case, if the auto-reload function is enabled, timer c is initialized to its initial value; if auto-reload is disabled, the timer is initialized to $00. the overflow sets the timer c interrupt request flag (iftc: $002, bit 2). timer c also functions as a watchdog timer. if a program routine runs out of control and an overflow is generated while the watchdog on (wdon) flag is set, the mcu is reset. this error can be detected by having the program control timer c reset before timer c reaches $ff. the wdon can only have 1 written to it; it is cleared to 0 only by mcu reset. timer/counter c (tcc) ? ? ? ? ? ? ? ? 2 4 8 32 128 512 1024 2048 selector system clock per prescaler s (pss) 3 timer load register c lower (tcrl) timer mode register c (tmc) timer load register c upper (tcru) clock free-running/ reload timer control signal timer latch register c (tlc) interrupt request flag of timer c (iftc) overflow watchdog timer controller watchdog on flag (wdon) system reset signal internal data bus figure 28 timer c block diagram
hd404328 series 48 timer mode register a (tma: $008): four-bit write-only register that controls timer a as shown in table 24. table 24 timer mode register a tma bit 3 bit 2 bit 1 bit 0 source prescaler, input clock period, operating mode 0 0 0 0 pss, 2048 t cyc timer a mode 1 pss, 1024 t cyc 1 0 pss, 512 t cyc 1 pss, 128 t cyc 1 0 0 pss, 32 t cyc 1 pss, 8 t cyc 1 0 pss, 4 t cyc 1 pss, 2 t cyc 1 0 0 0 psw, 32 t subcyc time-base mode 1 psw, 16 t subcyc 1 0 psw, 8 t subcyc 1 psw, 2 t subcyc 1 0 0 psw, 1/2 t subcyc 1 do not use 1 0 psw, tca reset 1 notes: 1. t subcyc = 244.14 m s (when 32.768-khz crystal oscillator is used) 2. t cyc = 1.9074 m s (when 4.1943-mhz crystal oscillator is used) 3. timer counter overflow output period (seconds) = input clock period (seconds) 256. 4. if psw or tca reset is selected while the lcd is operating, lcd operation halts (power switch goes off and all seg and com pins are grounded). when an lcd is connected for display, the psw and tca reset periods must be set in the program to the minimum. 5. the division ratio must not be modified during time-base mode operation, otherwise an overflow cycle error will occur. timer mode register b (tmb: $009): four-bit write-only register that selects the auto-reload function, input clock source, and the prescaler division ratio as shown in table 25. it is initialized to $0 by mcu reset. writing to this register is valid from the second instruction execution cycle. timer b initialization set by writing to tmb must be done after a mode change becomes valid.
hd404328 series 49 table 25 timer mode register b tmb bit 3 auto reload function 0 disabled 1 enabled tmb bit 2 bit 1 bit 0 input clock period/ input clock source 0 0 0 2048 t cyc 1 512 t cyc 1 0 128 t cyc 1 32 t cyc 1008 t cyc 14 t cyc 1 0 2 t cyc 1 zcd/ event (external event input) timer mode register c (tmc: $00d): four-bit write-only register that selects the auto-reload function and prescaler division ratio as shown in table 26. it is initialized to $0 by mcu reset. writing to this register is valid from the second instruction execution cycle. timer c initialization set by writing to tmc must be done after a mode change becomes valid. table 26 timer mode register c tmc bit 3 auto reload function 0 disabled 1 enabled
hd404328 series 50 tmc bit 2 bit 1 bit 0 input clock period 0 0 0 2048 t cyc 1 1024 t cyc 1 0 512 t cyc 1 128 t cyc 1 0 0 32 t cyc 18 t cyc 1 0 4 t cyc 12 t cyc pulse output the mcu has a built-in pulse output function called buzz. the pulse frequency can be selected from the prescaler s s outputs, and the output frequency depends on the state of port mode register c (pmrc: $012), as shown in table 27. the duty cycle of the pulse output is fixed at 50%. when the pulse output function is used, the r1 3 /buzz pin must be specified as buzz by pmrc. table 27 port mode register c pmrc bit 1 bit 0 prescaler division ratio 00 ? 1024 1 ? 512 10 ? 256 1 ? 128
hd404328 series 51 serial interface the mcu has a clock-synchronous serial interface which transmits and receives 8-bit data. the serial interface consists of a serial data register (sr), serial mode register (smr), port mode register a (pmra), octal counter, and selector, as shown in figure 29. the r1 0 / sck pin and the transmit clock are controlled by writing data to the smr. the transmit clock shifts the contents of the sr, which can be read and written to by software, before transmission starts between two mcus. the serial interface is activated by the sts instruction. the octal counter is reset to 000 by this instruction, it starts counting at the falling edge of the transmit clock ( sck ), and it increments at the rising edge of the clock. a serial interrupt request flag is set when the eighth transmit clock signal is input (the serial interface is reset) or when serial transmission is discontinued (the octal counter is reset). internal data bus ? ? ? ? ? ? 2 8 32 128 512 2048 sck selector system clock per prescaler s (pss) 3 serial mode register (smr) clock serial data register (sr) serial interrupt request flag (ifs) selector 1/2 si so octal counter (oc) i/o controller transfer control signal figure 29 serial interface block diagram serial mode register (smr: $005): four-bit write-only register that controls the r1 0 / sck pin, transmit clock, and prescaler division ratio as shown in figure 30. writing to this register initializes the serial interface. a write signal input to the serial mode register discontinues the input of the transmit clock to the serial data register and octal counter. therefore, if a write is performed during data transmission, the octal counter is reset to 000 to stop transmission, and, at the same time, the serial interrupt request flag is set.
hd404328 series 52 write operations are valid from the second instruction execution cycle, so the sts instruction must be executed after at least two cycles have been executed. the serial mode register is initialized to $0 by mcu reset. serial mode register (smr): $005 3210 transmit clock selection r1 / sck pin mode selection 0 smr bit 3 r1 / sck pin 0 0 1 r1 port input or output pin sck input or output pin 0 smr bit 2 bit 1 bit 0 r1 / sck pin 0 clock source prescaler division ratio transmit clock period 00 1 0 1 0 1 0 1 0 1 1 0 1 sck output sck output sck output sck output sck output sck output sck output sck input prescaler prescaler prescaler prescaler prescaler prescaler system clock external clock 2048 512 128 32 8 2 ? 4096 t 1024 t 256 t 64 t 16 t 4 t 1 t cyc cyc cyc cyc cyc cyc cyc note: t = 1.9074 s (with 4.1943-mhz crystal oscillator used at 1/8 division ratio) cyc initial value: 0000, r/w: w figure 30 serial mode register serial data register (srl: $006, sru: $007): eight-bit read/write register separated into upper and lower digits located at sequential addresses. data in this register is output from the so pin, lsb first, in synchronism with the falling edge of the transmit clock; and data is input, lsb first, through the si pin at the rising edge of the transmit clock. input/output timing is shown in figure 31. data cannot be read or written during serial data transmission. if a read/write occurs during transmission, the accuracy of the resultant data cannot be guaranteed.
hd404328 series 53 transmit clock 12345678 lsb msb serial output data serial input data latch timing figure 31 timing of serial interface output selecting and changing operating mode: table 28 lists the serial interface? operating modes. to select an operating mode, use one of these combinations of pmr and smr settings; to change the operating mode, always initialize the serial interface internally by writing data to the smr. table 28 serial interface operating modes smr pmra bit 3 bit 1 bit 0 operating mode 1 0 0 continuous clock output mode 1 transmit mode 1 0 receive mode 1 transmit/receive mode serial interface operation: three operating modes are provided for the serial interface; transitions between them are shown in figure 32. in sts wait state, the serial interface is initialized and the transmit clock is ignored. if the sts instruction is then executed, the serial interface enters transmit clock wait state. in transmit clock wait state, input of the transmit clock increments the octal clock, shifts the serial clock register, and activates serial transmission. however, note that if clock output mode is selected, the transmit clock is continuously output but data is not transmitted. during transfer state, the input of eight clocks or the execution of the sts instruction sets the octal counter to 000, and the serial interface enters transmit clock wait state. if the state changes from transmit to another state, the serial interrupt request flag is set by the octal counter reaching 000. in this state, if the internal clock has been selected, the transmit clock is output in answer to the execution of the sts instruction, but serial transmission is inhibited after the eighth clock is output.
hd404328 series 54 if port mode register a (pmra) is written to in transmit clock wait state or transfer state, the serial mode register (smr) must be written to, to initialize the serial interface. the serial interface then enters sts wait state. if the serial interface shifts from transfer state to another state, the octal counter returns to 000, setting the serial interrupt request flag. sts instruction wait state (octal counter = 000, transmit clock disabled) transfer state (octal counter 000) transmit clock wait state (octal counter = 000) sts instruction smr write transmit clock 8 transmit clocks (external clock) sts instruction (ifs ? 1) 8 transmit clocks (internal clock) (ifs ? 1) smr write (ifs ? 1) 1 figure 32 serial interface mode transitions transmit clock error detection: the serial interface will malfunction if a spurious pulse caused by external noise conflicts with a normal transmit clock during transmission. a transmit clock error of this type can be detected as shown in figure 33. if more than eight transmit clocks are input in transmit clock wait state, the serial interface? state changes to transfer, transmit clock wait, then back to transfer. if the serial interface is set to sts wait state by writing data to the smr after the serial interrupt request flag has been reset, the flag is reset again.
hd404328 series 55 transmission completion (ifs ? 1) interrupts inhibited ifs ? 0 smr write ifs = 1? normal termination yes no transmit clock error processing figure 33 transmit clock error detection note on use: the serial interrupt request flag might not be set if the status is changed from transfer by the execution of an smr write or sts instruction during the first period that the transmit clock is low. to prevent this, program a check that the sck pin is at 1 (by executing an input instruction for the r1 port) before the execution of an smr write or sts instruction, to ensure that the serial interrupt request flag is set.
hd404328 series 56 a/d converter the mcu has a built-in a/d converter that uses a sequential comparison method with a resistor ladder. it can measure four analog inputs with an eight-bit resolution. as shown in the block diagram of figure 34, the a/d converter has a four-bit a/d mode register, a one-bit a/d start flag, and a four-bit plus four-bit a/d data register. 4 4 4 comparator operation mode signal (stop mode, watch mode, subactive mode: value is 0) an 0 av 1 2 1 internal bus line (s2) internal bus line (s1) a/d mode register (amr: $016) a/d start flag (adsf: $020) a/d data register (adrl: $017, adru: $018) control logic counter ifad selector + ? an 1 an 2 an 3 cc av ss 1 figure 34 a/d converter block diagram a/d mode register (amr: $016): four-bit write-only register which selects the a/d conversion period and indicates analog input pin information. bit 0 of the amr selects the a/d conversion period, and bits 2 and 3 select a channel, as shown in figure 35. a/d start flag (adsf: $020, bit 2): one-bit flag that initiates a/d conversion when 1 is written to it. at the completion of a/d conversion, the converted data is stored in the a/d data register and the adsf is cleared. refer to figure 35. note: use the sem and semd instructions to write data to the adsf, but make sure that the adsf is not written to during a/d conversion.
hd404328 series 57 a/d mode register (amr): $016 32 10 switching time not used analog input selection switching time amr bit 0 0 1 34 t 67 t cyc cyc analog input selection an an an an 0 1 2 3 1 amr bit 3 0 1 bit 2 0 1 0 1 special flag bits: $020 lson (refer to description of low-power dissipation modes) wdon (refer to description of timers) a/d start flag (adsf) dton (refer to description of low-power dissipation modes) bit 2 1 0 a/d start flag (adsf) a/d conversion started a/d conversion completed 32 10 initial value: 0000, r/w: w figure 35 a/d registers a/d data register (adrl: $017, adru: $018): eight-bit read-only register that is not cleared by a reset. note that data read from this register during a/d conversion cannot be guaranteed. after the completion of a/d conversion, the resultant eight-bit data is held in this register, as shown in figure 36, until the start of the next conversion.
hd404328 series 58 adru: $018 adrl: $017 bit 7 bit 0 result 32 10 32 10 lsb msb figure 36 a/d data registers note on use: the contents of the a/d data register are not guaranteed during a/d conversion. to ensure that the a/d converter operates stably, do not execute port output instructions during a/d conversion.
hd404328 series 59 lcd controller/driver the mcu has an lcd controller and driver which drive four common signal pins and 24 segment pins. the controller consists of a ram area in which display data is stored, a display control register (lcr), and a duty cycle/clock control register (lmr), as shown in figures 37 and 38. four duty cycles and the lcd clock are program-controllable, and a built-in dual-port ram ensures that display data can be automatically transmitted to the segment signal pins without program intervention. if a 32-khz oscillation clock is selected as the lcd clock source, the lcd can be used even in watch mode, in which the system clock stops. /seg16 3 power switch gnd display on/off duty cycle selection clock selection lcd clock divided system clock output divided 32-khz clock output seg17 seg24 v 1 v cc v 2 v 3 com1 com2 com3 com4 r2 /seg1 r2 /seg2 0 1 ram area $050 $067 12 lcd clock 22 3 1 4 lcd power control circuit lcd duty cycle/ clock control register (lmr: $014) lcd output register (lor: $015) display control register (lcr: $013) lcd segment driver segment/ r2?5 port multiplexer lcd common driver (dual-port ram) display area r5 * * * note: HD404324u, hd404326u, hd404328u and hd4074329u require external lcd voltage division resistors. lcd: liquid crystal display * figure 37 block diagram of lcd controller/driver
hd404328 series 60 lcd mode register (lmr): $014 lcd output register (lor): $015 lcd control register (lcr): $013 blank/display power switch on/off display on/off in watch mode or subactive mode (not used) duty cycle selection input clock selection r2/seg1?eg4 pin mode selection r3/seg5?eg8 pin mode selection r4/seg9?eg12 pin mode selection r5/seg13?eg16 pin mode selection 21 0 21 0 3 21 0 3 initial value: 000, r/w: w initial value: 0000, r/w: w initial value: 0000, r/w: w figure 38 lcd registers lcd data area and segment data ($050?067): as shown in figure 39, each bit of the storage area corresponds to one of four duty cycles. if data is written to an area corresponding to a certain duty cycle, it is automatically output to the corresponding segments as display data.
hd404328 series 61 80 81 82 83 84 85 86 87 88 89 90 91 bit 3 seg1 seg2 seg3 seg4 seg5 seg6 seg7 seg8 seg9 seg10 seg11 seg12 com4 $050 $051 $052 $053 $054 $055 $056 $057 $058 $059 $05a $05b bit 3 seg13 seg14 seg15 seg16 seg17 seg18 seg19 seg20 seg21 seg22 seg23 seg24 com4 bit 2 seg13 seg14 seg15 seg16 seg17 seg18 seg19 seg20 seg21 seg22 seg23 seg24 com3 bit 1 seg13 seg14 seg15 seg16 seg17 seg18 seg19 seg20 seg21 seg22 seg23 seg24 com2 bit 0 seg13 seg14 seg15 seg16 seg17 seg18 seg19 seg20 seg21 seg22 seg23 seg24 com1 $05c $05d $05e $05f $060 $061 $062 $063 $064 $065 $066 $067 bit 2 seg1 seg2 seg3 seg4 seg5 seg6 seg7 seg8 seg9 seg10 seg11 seg12 com3 bit 1 seg1 seg2 seg3 seg4 seg5 seg6 seg7 seg8 seg9 seg10 seg11 seg12 com2 bit 0 seg1 seg2 seg3 seg4 seg5 seg6 seg7 seg8 seg9 seg10 seg11 seg12 com1 92 93 94 95 96 97 98 99 100 101 102 103 figure 39 configuration of lcd ram area (for dual-port ram) lcd control register (lcr: $013): three-bit write-only register which controls lcd blanking, the turning on and off of the liquid-crystal display? power supply division resistor, and display in watch and subactive modes, as shown in table 29. blank/display blank: segment signals are turned off, regardless of lcd ram data setting. display: lcd ram data is output as segment signals. power switch on/off off: the power switch is off. on: the power switch is on and v 1 is v cc . watch/subactive mode display off: in watch and subactive modes, all common and segment pins are grounded and the liquid-crystal power switch is turned off. on: in watch and subactive modes, lcd ram data is output as segment signals.
hd404328 series 62 table 29 lcd control register lcr lcr lcr bit 2 display in watch mode or subactive mode bit 1 power switch on/off bit 0 blank/display 0 off 0 off 0 blank 1 on 1 on 1 display note: when using an lcd in watch mode or subactive mode, use the divided output of a 32-khz oscillator as the lcd clock and set bit 2 of the lcr to 1. if using the divided output of the system clock as the lcd clock, always set bit 2 of the lcr to 0. lcd duty cycle/clock control register (lmr: $014): four-bit write-only register which selects the display duty cycle and lcd clock source, as shown in table 30. the dependence of frame frequency on duty cycle is shown in table 31. table 30 lcd duty cycle/clock control register lmr bit 3 bit 2 bit 1 bit 0 duty selection/input clock selection 0 0 1/4 duty cycle 1 1/3 duty cycle 1 0 1/2 duty cycle 1 static 0 0 cl0 (32.768/64 khz when using a 32.768-khz oscillator) 1 cl1 (f cyc /256) 1 0 cl2 (f cyc /2048) 1 cl3 (refer to table 31) note: f cyc is the divided system clock output.
hd404328 series 63 table 31 lcd frame periods for different duty cycles static duty cycle lmr bit 3 bit 2 bit 3 bit 2 bit 3 bit 2 bit 3 bit 2 0 00110 11 instruction cycle time cl0 cl1 cl2 cl3 * 2 m s 512 hz 1953 hz 244 hz 122 hz/64 hz 1/2 duty cycle lmr bit 3 bit 2 bit 3 bit 2 bit 3 bit 2 bit 3 bit 2 0 00110 11 instruction cycle time cl0 cl1 cl2 cl3 * 2 m s 256 hz 976.5 hz 122 hz 61 hz/32 hz 1/3 duty cycle lmr bit 3 bit 2 bit 3 bit 2 bit 3 bit 2 bit 3 bit 2 0 00110 11 instruction cycle time cl0 cl1 cl2 cl3 * 2 m s 170.6 hz 651 hz 81.3 hz 40.6 hz/21.3 hz 1/4 duty cycle lmr bit 3 bit 2 bit 3 bit 2 bit 3 bit 2 bit 3 bit 2 0 00110 11 instruction cycle time cl0 cl1 cl2 cl3 * 2 m s 128 hz 488.2 hz 61 hz 30.5 hz/16 hz note: * the division ratio depends on the value of bit 3 of timer mode register a (tma); the first value is for tma3 = 0 and the second is for tma3 = 1. when tma3 = 0, cl3 = f cyc /4096 when tma3 = 1, cl3 = 32.768 khz/512.
hd404328 series 64 lcd output register (lor: $015): write-only register used to specify that ports r2?5 act as pins seg1?eg16, as shown in table 32. table 32 lcd output register lor lor lor lor bit 3 port selection bit2 port selection bit 1 port selection bit 0 port selection 0r50r40r30r2 1 seg16?eg13 1 seg12?eg9 1 seg8?eg5 1 seg4?eg1 large liquid-crystal panel drive and v lcd : to drive a large-capacity lcd, decrease the resistance of the built-in division resistors by attaching external resistors in parallel, as shown in figure 40. since hd404328u and hd4074329u do not have built-in division resistors, they require external lcd voltage division resistors for voltage adjustment. the size of these resistors cannot be simply calculated from the lcd load capacitance because the matrix configuration of the lcd complicates the paths of charge/discharge currents flowing through the capacitors?nd the resistance will also vary with lighting conditions. this size must be determined by trial-and-error, taking into account the power dissipation of the device using the lcd, but a resistance of 1 k w to 10 k w would usually be suitable. (another effective method is to attach capacitors of 0.1 m f to 0.3 m f.) always turn off the power switch (set bit 1 of the lcr to 0) before changing the liquid-crystal drive voltage (v lcd ).
hd404328 series 65 r r r v (v ) v v gnd cc 2 3 1 1 24 3-digit lcd com1 v cc v lcd seg1? seg24 v v v v gnd cc 1 2 3 static drive r r r v (v ) v v gnd cc 2 3 1 c c c v cc lcd 33 v gnd 2 24 6-digit lcd com1 com2 v cc v lcd seg1? seg24 v v v v gnd cc 1 2 3 1/2 duty cycle, 1/2 bias drive 3 24 8-digit lcd v cc v lcd seg1? seg24 v v v v gnd cc 1 2 3 1/3 duty cycle, 1/3 bias drive 4 24 12-digit lcd com1? com4 v cc v lcd seg1? seg24 v v v v gnd cc 1 2 3 1/4 duty cycle, 1/3 bias drive com1? com3 c = 0.1 f to 0.3 f figure 40 lcd connection examples
hd404328 series 66 zero-crossing detection circuit the mcu has a zero-crossing detection circuit that generates a digital signal in synchronism with an ac signal input to the zcd pin through an external capacitor. a block diagram of the zero-crossing detection circuit is shown in figure 41. the zero-crossing detection circuit has two modes (low sensitivity mode and high sensitivity mode) which are set by port mode register b (pmrb: $011) as shown in table 33. a digital signal generated by the zero-crossing detection circuit sets the zero-crossing interrupt request flag (ifzc). the interrupt edge is selected by the interrupt mode register (imr: $010). this signal can be made as the input clock of timer b by setting the input clock source of timer mode register b (tmb: $009) for external event input. note: after mcu reset, the d 8 /zcd/ event pin is set to zcd. with this setting, a supply current (bias current) always flows because a bias circuit within the zero-crossing circuit is still operating. this current flows in all mcu operation modes, but it is particularly critical in stop mode because the mcu is more affected by bias current since the other circuits of the lsi are not dissipating much current. if the zero-crossing detection function is not being used, use port mode register b to set this pin to d 8 or event . this prevents the bias current from flowing. d 8 port input ac input signal external capacitor event (refer to figure 27.) 2 2 d 8 /zcd/ interrupt mode register ifzc port mode register b mpx mpx zero-crossing detection circuit mpx mpx event pin figure 41 block diagram of zero-crossing detection circuit table 33 port mode register b pmrb 1 0 port selection 0 0 zcd (low sensitivity mode) 1 zcd (high sensitivity mode) * 10d 8 1 event note: * becomes low sensitivity in subactive mode.
hd404328 series 67 table 34 registers in special register area name address r/w bit description pmra $004 w 0 r1 2 /s0 pin mode selection 1r1 1 /si pin mode selection 2d 9 / int 0 pin mode selection 3d 10 /int 1 pin mode selection smr $005 w 2? serial transmit clock speed selection 3r1 0 / sck pin mode selection srl $006 r/w 3? serial interface data register, lower 4 bits sru $007 r/w 3? serial interface data register, upper 4 bits tma $008 w 2? input clock selection (timer a) 3 timer-a/time-base mode selection tmb $009 w 2? input clock selection (timer b) 3 auto-reload function selection tcbl/tlrl $00a r/w 3? timer counter/timer load register (timer b), lower 4 bits tcbu/tlru $00b r/w 3? timer counter/timer load register (timer b), upper 4 bits mis $00c w 1, 0 interrupt frame period selection 2r1 2 /so pmos off 3 changeover to setting by system oscillator frequency tmc $00d w 2? input clock selection (timer c) 3 auto-reload function selection tccl/tcrl $00e r/w 3? timer counter/timer load register (timer c), lower 4 bits tccu/tcru $00f r/w 3? timer counter/timer load register (timer c), upper 4 bits imr $010 w 1, 0 int 1 detection edge selection 3, 2 zero-crossing detection edge selection pmrb $011 w 1, 0 d 8 /zcd/ event pin mode selection 3, 2 do not use pmrc $012 w 1, 0 buzzer frequency selection 2r1 3 / buzz pin mode selection 3 pull-up mos transistor on/off selection lcr $013 w 0 lcd display selection 1 lcd power switch on/off selection 2 lcd display selection during watch mode 3 do not use lmr $014 w 1, 0 lcd duty cycle selection 3, 2 lcd input clock selection
hd404328 series 68 name address r/w bit description lor $015 w 0 r2/seg1?eg4 pin mode selection 1 r3/seg5?eg8 pin mode selection 2 r4/seg9?eg12 pin mode selection 3 r5/seg13?eg16 pin mode selection amr $016 w 0 conversion timing selection (a/d) 1 do not use 3, 2 analog input selection (a/d) adrl $017 r 3? a/d data register, lower 4 bits adru $018 r 3? a/d data register, upper 4 bits dcr0 $030 w 3? data control register for port r0 dcr1 $031 w 3? data control register for port r1 dcr2 $032 w 3? data control register for port r2 dcr3 $033 w 3? data control register for port r3 dcr4 $034 w 3? data control register for port r4 dcr5 $035 w 3? data control register for port r5 dcrb $03b w 3? data control register for port d 0 ? 3 dcrc $03c w 3? data control register for port d 4 ? 7 dcrd $03d w 0 data control register for port d 8 3? do not use
hd404328 series 69 prom mode description programming the built-in rom the mcu? built-in rom is programmed in prom mode in which the pins are arranged as shown in figure 42. prom mode is set by pulling test , m 0 , and m 1 low, and reset high as shown in figure 43. in prom mode, the mcu does not operate, but it can be programmed in the same way as any other commercial 27256-type eprom using a standard prom programmer and a 64-to-28?in socket adapter. recommended prom programmers and socket adapters are listed in table 35. since an hmcs400-series instruction is ten bits long, the hmcs400-series mcu has a built-in conversion circuit to enable use of a general-purpose prom programmer. this circuit splits each instruction into a lower five bits and an upper five bits that are read from or written to consecutive addresses. this means that if, for example, 16 kwords of built-in prom are to be programmed by a general-purpose prom programmer, a 32-kbyte address space ($0000?7fff) must be specified. v cc v v pp v cc ce 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 hd4074329s hd4074329us hd4074329c hd4074329fs hd4074329ufs 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 a 7 a 8 a 0 a 10 a 11 a 12 a 13 a 14 a 9 a 5 a 6 a 4 a 3 a 2 a 1 o 7 o 6 o 5 o 4 o 3 o 2 o 1 o 0 m 0 m 1 oe test gnd reset note: gnd gnd o 4 o 3 o 2 o 1 o 0 a 9 a 5 a 6 o 4 o 3 o 2 m 0 m 1 a 7 a 8 a 0 a 10 a 11 a 12 a 13 a 14 test gnd reset gnd gnd o 1 o 0 ce a 4 a 3 a 2 a 1 o 7 o 6 o 5 oe o 4 o 3 o 2 o 1 o 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 v pp v cc v v v v v v v v externally connect pins of the same name. this is not necessary if one of the sockets listed in table 35 is used. cc cc cc cc cc cc cc cc cc figure 42 pin arrangement in prom mode
hd404328 series 70 oe ce data o ? 07 address a ? 014 cc v v pp cc v gnd v pp o ? 07 a ? 014 reset test m 0 m 1 cc v oe ce figure 43 prom mode connections table 35 recommended prom programmers and socket adapters prom programmer socket adapter manufacturer model name package model name manufacturer data i/o corp. 29b dp-64s dc-64s hs432ess01h hitachi fp-64b hs432esf01h hitachi aval data corp. pkw-1000 dp-64s dc-64s hs432ess01h hitachi fp-64b hs432esf01h hitachi
hd404328 series 71 warnings 1. always specify addresses $0000 to $7fff when programming with a prom programmer. if address $8000 or higher is accessed, the prom may not be programmed or verified correctly. set all data in unused addresses to $ff. note that the plastic-package version cannot be erased and reprogrammed, but the ceramic window- package version can be reprogrammed after being exposed to ultraviolet light. 2. make sure that the prom programmer, socket adapter, and lsi are aligned correctly (their pin 1 positions match), otherwise overcurrents may damage the lsi. before starting programming, make sure that the lsi is firmly fixed in the socket adapter and the socket adapter is firmly fixed in the programmer. 3. prom programmers have two voltages (v pp ): 12.5 v and 21 v. remember that ztat ? devices require a v pp of 12.5 v?he 21-v setting will damage them. 12.5 v is the intel 27256 setting. programming and verification: the built-in prom of the mcu can be programmed at high speed without risk of voltage stress or damage to data reliability. programming and verification modes are selected as shown in table 36. for details of prom programming, refer to the notes on prom programming section. table 36 prom mode selection pin mode ce oe v pp o 0 ? 7 programming low high v pp data input verification high low v pp data output programming inhibited high high v pp high impedence erasure (window package) data in the prom is erased by exposing the lsi to ultraviolet light of a wavelength of 2537 ? for an integrated dose of at least 15 w.s/cm 2 . these conditions can be satisfied by placing the lsi about 2 cm to 3 cm away from an ultraviolet lamp with a rating of 12,000 m w/cm 2 for about 20 minutes. after erasure, all prom bits are set to 1. for details of packages with windows, refer to the notes on window packages section.
hd404328 series 72 addressing modes ram addressing modes the mcu has three ram addressing modes, as shown in figure 44 and described below. register indirect addressing mode: the contents of the w, x, and y registers (10 bits in total) are used as a ram address. direct addressing mode: a direct addressing instruction consists of two words. the first word contains the opcode, and the contents of the second word (10 bits) are used as a ram address. memory register addressing mode: the memory registers (mr), which consist of 16 digits from $040 $04f, are accessed with the lamr and xmra instructions. 1st word of instruction 2nd word of instruction direct addressing ram address memory register addressing instruction 0 0 1 0 0 0 register indirect addressing ram address ram address x 3 x 2 x 1 x 0 y 3 y 2 y 1 y 0 w w 0 1 w register x register y register ap 9 ap 8 ap 7 ap 6 ap 5 ap 4 ap 3 ap 21 ap 0 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 ap 9 ap 8 ap 7 ap 6 ap 5 ap 4 ap 3 ap 2 ap 1 ap 0 opcode m 3 m 2 m 1 m 0 opcode ap 9 ap 8 ap 7 ap 6 ap 5 ap 4 ap 3 ap 2 ap 1 ap 0 ap figure 44 ram addressing modes
hd404328 series 73 rom addressing modes and the p instruction the mcu has four rom addressing modes, as shown in figure 45 and described below. direct addressing mode: a program can branch to any address in the rom memory space by executing the jmpl, brl, or call instruction. each of these instructions replaces the 14 program counter bits (pc 13 ?c 0 ) with 14-bit immediate data. current page addressing mode: the mcu has 64 pages of rom with 256 words per page. a program can branch to any address in the current page by executing the br instruction. this instruction replaces the eight low-order bits of the program counter (pc 7 ?c 0 ) with eight-bit immediate data. if the br instruction is on a page boundary (address 256n + 255), executing that instruction transfers the pc contents to the next physical page, as shown in figure 47. this means that the execution of the br instruction on a page boundary will make the program branch to the next page. note that the hmcs400-series cross macroassembler has an automatic paging feature for rom pages. zero-page addressing mode: a program can branch to the zero-page subroutine area located at $000 $003f by executing the cal instruction. when the cal instruction is executed, 6 bits of immediate data are placed in the six low-order bits of the program counter (pc 5 ?c 0 ), and 0s are placed in the eight high- order bits (pc 13 ?c 6 ). table data addressing mode: a program can branch to an address determined by the contents of four- bit immediate data, the accumulator, and the b register by executing the tbr instruction. p instruction: rom data addressed in table data addressing mode can be referenced with the p instruction as shown in figure 46. if bit 8 of the rom data is 1, eight bits of rom data are written to the accumulator and the b register. if bit 9 is 1, eight bits of rom data are written to the r0 and r1 port output registers. if both bits 8 and 9 are 1, rom data is written to the accumulator and the b register, and also to the r0 and r1 port output registers at the same time. the p instruction has no effect on the program counter.
hd404328 series 74 current page addressing zero page addressing table data addressing 1st word of instruction 2nd word of instruction program counter [jmpl] [brl] [call] direct addressing instruction [br] [cal] [tbr] b register program counter a 5 a 4 a 3 a 2 a 1 a 0 pc 13 pc 12 pc 11 pc 10 pc 9 pc 8 pc 7 pc 6 pc 5 pc 4 pc 3 pc 2 pc 1 pc 0 opcode program counter p 3 p 2 p 1 p 0 b 3 b 2 b 1 b 0 a 3 a 2 a 1 a 0 opcode program counter instruction 0 0 0 0 0 0 0 0 instruction accumulator 0 0 pc 13 pc 12 pc 11 pc 10 pc 9 pc 8 pc 7 pc 6 pc 5 pc 4 pc 3 pc 2 pc 1 pc 0 p 3 p 2 p 1 p 0 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 opcode b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 opcode pc 13 pc 12 pc 11 pc 10 pc 9 pc 8 pc 7 pc 6 pc 5 pc 4 pc 3 pc 2 pc 1 pc 0 pc 13 pc 12 pc 11 pc 10 pc 9 pc 87 pc 65 pc 4 pc 3 pc pc 1 pc 0 pc pc 2 figure 45 rom addressing modes
hd404328 series 75 if ro = 1 8 address specification [p] b register referenced rom address instruction accumulator 0 0 rom data accumulator, b register output registers r0, r1 if ro = 1 9 rom data pattern output 3210321 r0 0 b 3 b 2 b 1 b 0 a 3 a 2 a 1 a 0 ra 13 ra 12 ra 11 ra 10 ra 9 ra 8 ra 7 ra 6 ra 5 ra 4 ra 3 ra 2 ra 1 ra 0 ro 9 ro 8 ro 7 ro 6 ro 5 ro 4 ro 3 ro 2 ro 1 ro 0 b 3 b 2 b 1 b 0 a 3 a 2 a 1 a 0 ro 9 ro 8 ro 7 ro 6 ro 5 ro 4 ro 3 ro 2 ro 1 ro 0 p 3 p 2 p 1 p 0 opcode r0 r0 r0 r1 r1 r1 r1 figure 46 p instruction br aaa aaa nop 256(n ?1) + 255 256n 256n + 254 256n + 255 256(n + 1) br br aaa bbb bbb nop figure 47 branching when branch destination is on a page boundary
hd404328 series 76 absolute maximum ratings item symbol value unit notes power voltage v cc ?.3 to +7.0 v programming voltage v pp ?.3 to +14.0 v 1 pin voltage v t ?.3 to v cc + 0.3 v total permissible input current ? i o 100 ma 2 total permissible output current ? i o 50 ma 3 maximum input current i o 4 ma 4, 5 30 ma 4, 6 maximum output current ? o 4 ma 7, 8 operating temperature t opr ?0 to +75 c storage temperature t stg ?5 to +125 c notes: permanent damage may occur if these absolute maximum ratings are exceeded. normal operation must be under the conditions stated in the electrical characteristics table. if these conditions are exceeded, the lsi may malfunction or its reliability may be affected. 1. d 10 (v pp ) of the hd4074329 and hd4074329u. 2. the total permissible input current is the total of input currents simultaneously flowing in from all the i/o pins to ground. 3. the total permissible output current is the total of output currents simultaneously flowing out from v cc to all i/o pins. 4. the maximum input current is the maximum current flowing from any i/o pin to ground. 5. applies to d 8 , r0?5. 6. applies to d 0 ? 7 . 7. the maximum output current is the maximum current flowing from v cc to any i/o pin. 8. applies to d 0 ? 8 , r0?5.
hd404328 series 77 electrical characteristics dc characteristics (HD404324, hd404326, hd404328: v cc = 2.7 v to 6.0 v, gnd = 0.0 v, t a = ?0 c to +75 c; HD404324u, hd404326u, hd404328u: v cc = 2.7 v to 6.0 v, gnd = 0.0 v, t a = ?0 c to +85 c; hd4074329, hd4074329u: v cc = 2.9 v to 5.5 v, gnd = 0.0 v, t a = ?0 cto+75 c; unless otherwise specified) item symbol pin(s) min typ max unit test conditions notes input high voltage v ih reset, sck , int 0 , int 1 , si, event 0.8v cc ? cc + 0.3 v HD404324, HD404324u: hd404326, hd404326u: hd404328, hd404328u: v cc = 3.5 v to 6.0 v hd4074329, hd4074329u: v cc = 3.5 v to 5.5 v 0.9v cc ? cc + 0.3 v osc 1 v cc ?0.5 v cc + 0.3 v HD404324, HD404324u: hd404326, hd404326u: hd404328, hd404328u: v cc = 3.5 v to 6.0 v hd4074329, hd4074329u: v cc = 3.5 v to 5.5 v v cc ?0.3 v cc + 0.3 v input low voltage v il reset, sck , int 0 , int 1 , event , si ?.3 0.2v cc v HD404324, HD404324u: hd404326, hd404326u: hd404328, hd404328u: v cc = 3.5 v to 6.0 v hd4074329, hd4074329u: v cc = 3.5 v to 5.5 v ?.3 0.1v cc v
hd404328 series 78 dc characteristics (HD404324, hd404326, hd404328: v cc = 2.7 v to 6.0 v, gnd = 0.0 v, t a = ?0 c to +75 c; HD404324u, hd404326u, hd404328u: v cc = 2.7 v to 6.0 v, gnd = 0.0 v, t a = ?0 c to +85 c; hd4074329, hd4074329u: v cc = 2.9 v to 5.5 v, gnd = 0.0 v, t a = ?0 cto+75 c; unless otherwise specified) (cont ) item symbol pin(s) min typ max unit test conditions notes input low voltage v il osc 1 ?.3 0.5 v HD404324, HD404324u: hd404326, hd404326u: hd404328, hd404328u: v cc = 3.5 v to 6.0 v hd4074329, hd4074329u: v cc = 3.5 v to 5.5 v ?.3 0.3 v output high voltage v oh sck , so, buzz v cc ?1.0 v i oh = 0.5 ma output low voltage v ol sck , so, buzz 0.4 v i ol = 0.4 ma i/o leakage current |i il | reset, sck , int 0 , int 1 , si, so, osc 1 , buzz 1.0 m av in = 0 to v cc 1 current dissipation in active mode i cc v cc ?6 mav cc = 5.0 v, f osc = 4 mhz 2 current dissipation in standby mode i sby v cc 0.6 1.5 ma v cc = 3.0 v, lcd on 3 current dissipation in subactive mode i sub v cc ?070 m a HD404324, hd404326, hd404328: v cc = 3.0 v, lcd on ?060 m a HD404324u, hd404326u, hd404328u: v cc = 3.0 v, lcd on 70 150 m a hd4074329: v cc = 3.0 v, lcd on 60 140 m a hd4074329u: v cc = 3.0 v, lcd on current dissipation in watch mode(1) i wtc1 v cc ?15 m av cc = 3.0 v, lcd off 4
hd404328 series 79 dc characteristics (HD404324, hd404326, hd404328: v cc = 2.7 v to 6.0 v, gnd = 0.0 v, t a = ?0 c to +75 c; HD404324u, hd404326u, hd404328u: v cc = 2.7 v to 6.0 v, gnd = 0.0 v, t a = ?0 c to +85 c; hd4074329, hd4074329u: v cc = 2.9 v to 5.5 v, gnd = 0.0 v, t a = ?0 c to +75 c; unless otherwise specified) (cont ) item symbol pin(s) min typ max unit test conditions notes current dissipation in watch mode(2) i wtc2 v cc ?535 m a HD404324, hd404326, hd404328, hd4074329: v cc = 3.0 v, lcd on 4 ?25 m a HD404324u, hd404326u, hd404328u, hd4074329u: v cc = 3.0 v, lcd on 4 current dissipation in stop mode i stop v cc ?10 m av cc = 3.0 v, x1 = v cc 4 stop mode retain voltage v stop v cc 2 v no 32-khz oscillator 5 notes: 1. output buffer current is excluded. 2. i cc1 is the source current when no i/o current is flowing while the mcu is in reset state. test conditions: mcu: reset pins: reset, test , d 0 ? 7 , d 9 , d 10 , r0?5 at v cc d 8 open 3. i sby is the source current when no i/o current is flowing while the mcu timer is in operation. test conditions: mcu: i/o reset serial interface stopped standby mode pins: reset at gnd test , d 0 ? 7 , d 9 , d 10 , r0?5 at v cc d 8 open 4. d 10 is connected to v cc in the hd4074329 and hd4074329u. 5. ram data retention.
hd404328 series 80 i/o characteristics for standard pins (HD404324, hd404326, hd404328: v cc = 2.7 v to 6.0 v, gnd = 0.0 v, t a = ?0 c to +75 c; HD404324u, hd404326u, hd404328u: v cc = 2.7 v to 6.0 v, gnd = 0.0 v, t a = ?0 c to +85 c; hd4074329, hd4074329u: v cc = 2.9 v to 5.5 v, gnd = 0.0 v, t a = ?0 c to +75 c; unless otherwise specified) item symbol pin(s) min typ max unit test conditions note input high voltage v ih d 8 ? 10 , r0?5 0.7v cc ? cc + 0.3 v input low voltage v il d 8 ? 10 , r0?5 ?.3 0.3v cc v output high voltage v oh d 8 , r0?5 v cc ?1.0 v i oh = 0.5 ma output low voltage v ol d 8 , r0?5 0.4 v i ol = 0.4 ma i/o leakage current |i il |d 8 , d 9 , r0?5 1.0 m av in = 0 to v cc * d 10 1.0 m a HD404324, HD404324u, hd404326, hd404326u, hd404328, hd404328u: v in = 0 to v cc * 20.0 m a hd4074329, hd4074329u v in = 0 to v cc pull-up mos current ? pu d 8 , r0?5 5 25 90 m av cc = 3.0 v, v in = 0.0 v note: * output buffer current is excluded.
hd404328 series 81 i/o characteristics for high-current pins (HD404324, hd404326, hd404328: v cc = 2.7 v to 6.0 v, gnd = 0.0 v, t a = ?0 c to +75 c; HD404324u, hd404326u, hd404328u: v cc = 2.7 v to 6.0 v, gnd = 0.0 v, t a = ?0 c to +85 c; hd4074329, hd4074329u: v cc = 2.9 v to 5.5 v, gnd = 0.0 v, t a = ?0 c to +75 c; unless otherwise specified) item symbol pin(s) min typ max unit test conditions note input high voltage v ih d 0 ? 7 0.7v cc ? cc + 0.3 v input low voltage v il d 0 ? 7 ?.3 0.3v cc v output high voltage v oh d 0 ? 7 v cc ?1.0 v i oh = 0.5 ma output low voltage v ol d 0 ? 7 0.4 v i ol = 0.4 ma 2.0 v HD404324, HD404324u, hd404326, hd404326u, hd404328, hd404328u: i ol = 15 ma, v cc = 4.5 v to 6.0 v hd4074329, hd4074329u: i ol = 15 ma, v cc = 4.5 v to 5.5 v i/o leakage current |i il |d 0 ? 7 1.0 m av in = 0 to v cc * pull-up mos current ? pu d 0 ? 7 52590 m av cc = 3.0, v in = 0 note: * output buffer current is excluded.
hd404328 series 82 lcd circuit characteristics (HD404324, hd404326, hd404328: v cc = 2.7 v to 6.0 v, gnd = 0.0 v, t a = ?0 c to +75 c; HD404324u, hd404326u, hd404328u: v cc = 2.7 v to 6.0 v, gnd = 0.0 v, t a = ?0 c to +85 c; hd4074329, hd4074329u: v cc = 2.9 v to 5.5 v, gnd = 0.0 v, t a = ?0 c to +75 c; unless otherwise specified) item symbol pin(s) min typ max unit test conditions note segment driver voltage drop v ds seg1?eg24 0.6 v i d = 3.0 m a1 common driver voltage drop v dc com1?om4 0.3 v i d = 3.0 m a1 lcd power supply division resistor r w 100 300 900 k w HD404324, hd404326, hd404328, hd4074329: between v 1 and gnd, v 1 = v cc lcd voltage v lcd v 1 2.7 v cc v HD404324, HD404324u, hd404326, hd404326u, hd404328, hd404328u 2 2.9 v cc v hd4074329, hd4074329u 2 notes: 1. v ds and v dc are the voltage drops from power supply pins v 1 , v 2 , and v 3 , and gnd to each segment pin and each common pin. 2. when v lcd is supplied from an external source, the following relations must be retained: v cc 3 v 1 3 v 2 3 v 3 3 gnd
hd404328 series 83 a/d converter characteristics (HD404324, hd404326, hd404328: v cc = 2.7 v to 6.0 v, av ss = 0.0 v, t a = ?0 c to +75 c; HD404324u, hd404326u, hd404328u: v cc = 2.7 v to 6.0 v, av ss = 0.0 v, t a = ?0 c to +85 c; hd4074329, hd4074329u: v cc = 2.9 v to 5.5 v, av ss = 0.0 v, t a = ?0 c to +75 c; unless otherwise specified) item symbol pin(s) min typ max unit test conditions note analog power voltage av cc av cc v cc ?0.3 v cc v cc + 0.3 v analog input voltage av in an 0 ?n 3 av ss ?v cc v current between av cc and av ss i ad 50 m av cc = av cc = 5.0 v analog input capacitance ca in an 0 ?n 3 ?0 pf resolution 8 8 8 bit number of inputs 0 4 cha nnel absolute accuracy 2.0 lsb * conversion period 34 67 t cyc analog input impedance an 0 ?n 3 1m w f = 1 mhz, v in = 0.0 v note: * operating frequency of a/d conversion f osc is from 1 (mhz) to 4.5 (mhz). zero-crossing detection circuit characteristics low sensitivity mode (HD404324, HD404324u, hd404326, hd404326u, hd404328, hd404328u: v cc = 2.7 v to 6.0 v, gnd = 0.0 v, t a = 0 c to +70 c; hd4074329, hd4074329u: v cc = 3.0 v to 5.5 v, gnd = 0.0 v, t a = 0 c to +70 c; unless otherwise specified) item symbol pin min typ max unit test conditions note zero-crossing detection input voltage v zc zcd 2.0 3.0 v p-p ac connection, c = 0.1 m f zero-crossing detection accuracy v azc 750 mv f zc = 50/60 hz (sine wave), f osc = 4 mhz refer to figure 48 zero-crossing detection input frequency f zc 45 250 hz
hd404328 series 84 high sensitivity mode (v cc = 5.0 v, gnd = 0.0 v, t a = 0 c to 70 c, unless otherwise specified) item symbol pin min typ max unit test conditions note zero-crossing detection input voltage v zc zcd 2.0 3.0 v p-p ac connection, c = 0.1 m f zero-crossing detection accuracy v azc 100 mv f zc = 50/60 hz (sine wave), f osc = 4 mhz, v cc = 5.0 v refer to figure 48 zero-crossing detection input frequency f zc 45 1000 hz ac input internal cpu signal the internal cpu signal is shown lagging behind the original waveform in the figure, but this is not fixed?t could actually lead. 1/f zc v azc v zc(p-p) v azc note: figure 48 zero-crossing detection
hd404328 series 85 ac characteristics (HD404324, hd404326, hd404328: v cc = 2.7 v to 6.0 v, gnd = 0.0 v, t a = ?0 c to +75 c; HD404324u, hd404326u, hd404328u: v cc = 2.7 v to 6.0 v, gnd = 0.0 v, t a = ?0 c to +85 c; hd4074329, hd4074329u: v cc = 2.9 v to 5.5 v, gnd = 0.0 v, t a = ?0 c to +75 c; unless otherwise specified) item symbol pin(s) min typ max unit test conditions note clock oscillation frequency f osc osc 1 , osc 2 0.4 4.0 4.5 mhz 1/8 division, 32 khz used 1 0.4 4.0 4.5 mhz 1/8 division used, 32 khz not used x1, x2 32.768 khz instruction cycle time t cyc ? m sf osc = 4 mhz oscillation stabilization time(crystal) t rc osc 1 , osc 2 40 ms HD404324, HD404324u, hd404326, hd404326u, hd404328, hd404328u: v cc = 3.5 v to 6.0 v 2 hd4074329, hd4074329u: v cc = 3.5 v to 5.5 v 60 ms 2 oscillation stabilization time(ceramic) t rc osc 1 , osc 2 20 ms HD404324, HD404324u, hd404326, hd404326u, hd404328, hd404328u: v cc = 3.5 v to 6.0 v 2 hd4074329, hd4074329u: v cc = 3.5 v to 5.5 v 60 ms 2 oscillation stabilization time t rc x1, x2 3 s 3 external clock high width t cph osc 1 90 ns 4 external clock low width t cpl osc 1 90 ns 4 external clock rise time t cpr osc 1 20 ns 4 external clock fall time t cpf osc 1 20 ns 4 int 0 , int 1 , event high width t ih int 0 , int 1 , event 2 t cyc / t subcyc 5 int 0 , int 1 , event width t il int 0 , int 1 , event 2 t cyc / t subcyc 5
hd404328 series 86 item symbol pin(s) min typ max unit test conditions note reset high width t rsth reset 2 f cyc 6 reset fall time t rstf reset 20 ms 6 input capacitance c in all pins except d 10 , an 0 ?n 3 30 pf f = 1 mhz, v in = 0.0 v d 10 30 pf HD404324, HD404324u, hd404326, hd404326u, hd404328, hd404328u: f = 1 mhz, v in = 0.0 v 180 pf hd4074329, hd4074329u: f = 1 mhz, v in = 0.0 v notes: 1. if f osc = 0.4 mhz to 1.0 mhz, bit 3 of the miscellaneous register (mis: $00c) must be set to 1; if f osc = 1.6 mhz to 4.5 mhz, bit 3 must be set to 0. do not use f osc = 1.0 mhz to1.6 mhz with 32- khz oscillation. 2. the oscillation stabilization time is the time required for the oscillator to stabilize after v cc reaches 2.7 v (2.9 v for the hd4074329 and hd4074329u, or 3.5 v if v cc = 3.5 v to 5.5 v) at power-on or after reset input goes high after stop mode is canceled. at power-on and when stop mode is cancelled, reset must be input for at least t rc to ensure the oscillation stabilization time. if using a crystal oscillator or a ceramic oscillator, contact its manufacturer to determine what stabilization time is required, since it will depend on the circuit constants and stray capacitances. 3. the oscillation stabilization time is the time required for the oscillator to stabilize after v cc reaches 2.7 v (2.9 v for the hd4074329 and hd4074329u) at power-on?t least t rc must be ensured. if using a 32.768-khz crystal oscillator, contact its manufacturer to determine what stabilization time is required, since it will depend on the circuit constants and stray capacitances. 4. refer to figure 49. 5. refer to figure 50. the t cyc unit applies when the mcu is in standby or active mode. the t subcyc unit applies when the mcu is in watch or subactive mode. t subcyc = 244.14 m s (32.768- khz crystal) 6. refer to figure 51.
hd404328 series 87 serial interface timing characteristics (HD404324, hd404326, hd404328: v cc = 2.7 v to 6.0 v, gnd = 0.0 v, t a = ?0 c to +75 c; HD404324u, hd404326u, hd404328u: v cc = 2.7 v to 6.0 v, gnd = 0.0 v, t a = ?0 c to +85 c; hd4074329, hd4074329u: v cc = 2.9 v to 5.5 v, gnd = 0.0 v, t a = ?0 c to +75 c; unless otherwise specified) during transmit clock output item symbol pin min typ max unit test conditions notes transmit clock cycle time t scyc sck 1.0 t cyc , t subcyc load shown in figure 53 1, 2 transmit clock high width t sckh sck 0.3 t scyc load shown in figure 53 1 transmit clock low width t sckl sck 0.3 t scyc load shown in figure 53 1 transmit clock rise time t sckr sck 100 ns HD404324, HD404324u, hd404326, hd404326u, hd404328, hd404328u: v cc = 3.5 v to 6.0 v, load shown in figure 53 1 hd4074329, hd4074329u: v cc = 3.5 v to 5.5 v, load shown in figure 53 1 200 ns load shown in figure 53 1 transmit clock fall time t sckf sck 100 ns HD404324, HD404324u, hd404326, hd404326u, hd404328, hd404328u: v cc = 3.5 v to 6.0 v, load shown in figure 53 1 hd4074329, hd4074329u: v cc = 3.5 v to 5.5 v, load shown in figure 53 1 200 ns load shown in figure 53 1 serial output data delay time t dso so 300 ns HD404324, HD404324u, hd404326, hd404326u, hd404328, hd404328u: v cc = 3.5 v to 6.0 v, load shown in figure 53 1 hd4074329, hd4074329u: v cc = 3.5 v to 5.5 v, load shown in figure 53 1 500 ns load shown in figure 53 1 notes: 1. refer to figure 52. 2. the t subcyc unit applies when subactive mode is operating.
hd404328 series 88 item symbol pin min typ max unit test conditions note serial input data setup time t ssi si 200 ns HD404324, HD404324u, hd404326, hd404326u, hd404328, hd404328u: v cc = 3.5 v to 6.0 v * hd4074329, hd4074329u: v cc = 3.5 v to 5.5 v * 300 ns * serial input data hold time t hsi si 150 ns HD404324, HD404324u, hd404326, hd404326u, hd404328, hd404328u v cc = 3.5 v to 6.0 v * hd4074329, hd4074329u v cc = 3.5 v to 5.5 v * 300 ns * note: * refer to figure 52.
hd404328 series 89 during transmit clock input item symbol pin min typ max unit test conditions notes transmit clock cycle time t scyc sck 1.0 t cyc , t subcyc 1, 2 transmit clock high width t sckh sck 0.3 t scyc 1 transmit clock low width t sckl sck 0.3 t scyc 1 transmit clock rise time t sckr sck 100 ns HD404324, HD404324u, hd404326, hd404326u, hd404328, hd404328u: v cc = 3.5 v to 6.0 v 1 hd4074329, hd4074329u: v cc = 3.5 v to 5.5 v 1 200 ns 1 transmit clock fall time t sckf sck 100 ns HD404324, HD404324u, hd404326, hd404326u, hd404328, hd404328u: v cc = 3.5 v to 6.0 v 1 hd4074329, hd4074329u: v cc = 3.5 v to 5.5 v 1 200 ns 1 serial output data delay time t dso so 300 ns HD404324, HD404324u, hd404326, hd404326u, hd404328, hd404328u: v cc = 3.5 v to 6.0 v, load shown in figure 53 1 hd4074329, hd4074329u: v cc = 3.5 v to 5.5 v, load shown in figure 53 1 500 ns load shown in figure 53 1 serial input data setup time t ssi si 200 ns HD404324, HD404324u, hd404326, hd404326u, hd404328, hd404328u: v cc = 3.5 v to 6.0 v 1 hd4074329, hd4074329u: v cc = 3.5 v to 5.5 v 1 300 ns 1 serial input data hold time t hsi si 150 ns HD404324, HD404324u, hd404326, hd404326u, hd404328, hd404328u: v cc = 3.5 v to 6.0 v 1 hd4074329, hd4074329u: v cc = 3.5 v to 5.5 v 1 300 ns 1 notes: 1. refer to figure 52. 2. the t subcyc unit applies when subactive mode is operating.
hd404328 series 90 osc 1 0.3 v v ?0.3 v cc cpr t 0.5 v 1/f cp t cpl t cpf v ?0.5 v cc osc 1 t cph cpr t 1/f cp t cpl t cpf v = 3.5 v to 6.0 v (HD404324, HD404324u, hd404326, hd404326u, hd404328, hd404328u) v = 3.5 v to 5.5 v (hd4074329, hd4074329u) cc cc v = 2.7 v to 3.5 v (HD404324, HD404324u, hd404326, hd404326u, hd404328, hd404328u) v = 2.9 v to 3.5 v (hd4074329, hd4074329u) cc cc t cph figure 49 oscillator timing v = 2.7 v to 3.5 v ( HD404324, HD404324u, hd404326, hd404326u, hd404328, hd404328u ) v = 2.9 v to 3.5 v (hd4074329, hd4074329u) cc cc il t ih t int , int , 01 0.8v cc v = 3.5 v to 6.0 v ( HD404324, HD404324u, hd404326, hd404326u, hd404328, hd404328u ) v = 3.5 v to 5.5 v (hd4074329, hd4074329u) cc cc 0.2v cc 0.9v cc 0.1v cc il t ih t int , int , 01 event event figure 50 interrupt timing
hd404328 series 91 v = 2.7 v to 3.5 v ( HD404324, HD404324u, hd404326, hd404326u, hd404328, hd404328u ) v = 2.9 v to 3.5 v (hd4074329, hd4074329u) cc cc 0.8v cc v = 3.5 v to 6.0 v ( HD404324, HD404324u, hd404326, hd404326u, hd404328, hd404328u ) v = 3.5 v to 5.5 v (hd4074329, hd4074329u) cc cc 0.2v cc reset rstf t rsth t 0.9v cc 0.1v cc reset rstf t rsth t figure 51 reset timing
hd404328 series 92 sckf t 0.8v cc v = 3.5 v to 6.0 v ( HD404324, HD404324u, hd404326, hd404326u, hd404328, hd404328u ) v = 3.5 v to 5.5 v (hd4074329, hd4074329u) cc cc 0.2v cc so si 0.8 v 0.8 v (0.2v ) cc v ?2.0 v cc v ?2.0 v (0.8v ) cc cc dso t scyc t sckl t sckr t sckh t ssi t hsi t sck v ?2.0 v and 0.8 v are the threshold voltages for transmit clock output, 0.8v and 0.2v are the threshold voltages for transmit clock input, and t , t , and t are the timings used with transmit clock input voltages. cc dso ssi hsi cc cc sckf t 0.9v cc v = 2.7 v to 3.5 v ( HD404324, HD404324u, hd404326, hd404326u, hd404328, hd404328u ) v = 2.9 v to 3.5 v (hd4074329, hd4074329u) cc cc 0.1v cc so si 0.4 v 0.4 v (0.1v ) cc v ?0.5 v cc v ?0.5 v (0.9v ) cc cc dso t scyc t sckl t sckr t sckh t ssi t hsi t sck v ?0.5 v and 0.4 v are the threshold voltages for transmit clock output, 0.9v and 0.1v are the threshold voltages for transmit clock input, and t , t , and t are the timings used with transmit clock input voltages. cc dso ssi hsi cc cc * * * note: * * * note: sckhd t sckhd t figure 52 serial interface timing v cc r c r = 2.6 k l 30 pf 12 k test point 1s2074 h or equivalent w figure 53 timing load circuit
hd404328 series 93 option list HD404324, HD404324li, hd404326, hd404326u, hd404328, hd404328u please check off the appropriate applications and enter the necessary information. 6. stop mode used not used lsi number (to be filled in by hitachi) date of order customer department rom code name / / 2. optional function (1) with 32-khz cpu operation without 32-khz cpu operation, with time-base for clock without 32-khz cpu operation, without time-base HD404324 hd404326 hd404328 HD404324u hd404326u hd404328u 4-kword 6-kword 8-kword 4-kword 6-kword 8-kword with internal lcd voltage division registers without internal lcd voltage division registers 4. rom code media eprom: 5. system oscillator for osc1 and osc2 ceramic oscillator crystal oscillator external clock f = f = f = mhz mhz mhz * * note: the upper bits and lower bits are mixed together. the upper five bits and lower five bits are programmed to the same eprom in alternating order (i.e., lululu...). eprom: the upper bits and lower bits are separated. the upper five bits and lower five bits are programmed to different eproms. * 3. optional function (2) with zero-crossing detection function without zero-crossing detection function options marked with an asterisk require a subsystem crystal oscillator (x1, x2). please specify the first type below (the upper bits and lower bits are mixed together), when using the eprom on-package microcomputer type (including ztat version). 7. packages dp-64s fp-64a fp-64b 1. rom size
hd404328 series 94 cautions 1. hitachi neither warrants nor grants licenses of any rights of hitachi? or any third party? patent, copyright, trademark, or other intellectual property rights for information contained in this document. hitachi bears no responsibility for problems that may arise with third party? rights, including intellectual property rights, in connection with use of the information contained in this document. 2. products and product specifications may be subject to change without notice. confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. hitachi makes every attempt to ensure that its products are of high quality and reliability. however, contact hitachi? sales office before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. design your application so that the product is used within the ranges guaranteed by hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail- safes, so that the equipment incorporating hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the hitachi product. 5. this product is not designed to be radiation resistant. 6. no one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from hitachi. 7. contact hitachi? sales office for any questions regarding this document or hitachi semiconductor products. hitachi, ltd. semiconductor & integrated circuits. nippon bldg., 2-6-2, ohte-machi, chiyoda-ku, tokyo 100-0004, japan tel: tokyo (03) 3270-2111 fax: (03) 3270-5109 copyright ?hitachi, ltd., 1998. all rights reserved. printed in japan. hitachi asia pte. ltd. 16 collyer quay #20-00 hitachi tower singapore 049318 tel: 535-2100 fax: 535-1533 url northamerica : http:semiconductor.hitachi.com/ europe : http://www.hitachi-eu.com/hel/ecg asia (singapore) : http://www.has.hitachi.com.sg/grp3/sicd/index.htm asia (taiwan) : http://www.hitachi.com.tw/e/product/sicd_frame.htm asia (hongkong) : http://www.hitachi.com.hk/eng/bo/grp3/index.htm japan : http://www.hitachi.co.jp/sicd/indx.htm hitachi asia ltd. taipei branch office 3f, hung kuo building. no.167, tun-hwa north road, taipei (105) tel: <886> (2) 2718-3666 fax: <886> (2) 2718-8180 hitachi asia (hong kong) ltd. group iii (electronic components) 7/f., north tower, world finance centre, harbour city, canton road, tsim sha tsui, kowloon, hong kong tel: <852> (2) 735 9218 fax: <852> (2) 730 0281 telex: 40815 hitec hx hitachi europe ltd. electronic components group. whitebrook park lower cookham road maidenhead berkshire sl6 8ya, united kingdom tel: <44> (1628) 585000 fax: <44> (1628) 778322 hitachi europe gmbh electronic components group dornacher stra? 3 d-85622 feldkirchen, munich germany tel: <49> (89) 9 9180-0 fax: <49> (89) 9 29 30 00 hitachi semiconductor (america) inc. 179 east tasman drive, san jose,ca 95134 tel: <1> (408) 433-1990 fax: <1>(408) 433-0223 for further information write to:

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